Rxx_MASTERS Region Masters Register

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)
Document ID
XAPP1353
Release Date
2022-05-04
Revision
1.1 English

The AXI_MasterID from the requester is compared with all authorized secure MasterIDs for the region addressed. If the originating master is authorized: False, transaction is poisoned; if it is True, transaction is forwarded downstream.

Note: Address Offset: 0x00000[n]08
Note: PMU is always authorized by default.

The R[n]_MASTERS register is shown in the following table.

Table 1. R[n]_MASTERS (XMPU_PL) Register Bit Field Summary
Field Name Bits Type Reset Value Description
Reserved 31 ro 0x0 Reserved
MID_FPD_DMA[6:7] 30 rw 0x0 Enable FPD DMA [ch 6:7]
MID_FPD_DMA[4:5] 29 rw 0x0 Enable FPD DMA [ch 4:5]
MID_FPD_DMA[2:3] 28 rw 0x0 Enable FPD DMA [ch 2:3]
MID_FPD_DMA[0:1] 27 rw 0x0 Enable FPD DMA [ch 0:1]
MID_DP_DMA[4:5] 26 rw 0x0 Enable DisplayPort DMA [ch 4:5]
MID_DP_DMA[2:3] 25 rw 0x0 Enable DisplayPort DMA [ch 2:3]
MID_DP_DMA[0:1] 24 rw 0x0 Enable DisplayPort DMA [ch 0:1]
MID_PCIE 23 rw 0x0 Enable PCIe
MID_DAP_AXI 22 rw 0x0 Enable Debug Access Port AXI
MID_GPU 21 rw 0x0 Enable GPU
MID_SATA1 20 rw 0x0 Enable SATA1
MID_SATA0 19 rw 0x0 Enable SATA0
MID_APU 18 rw 0x0 Enable APU.
Note: Requires that AxProt[1]=0.
MID_GEM3 17 rw 0x0 Enable GEM3
MID_GEM2 16 rw 0x0 Enable GEM2
MID_GEM1 15 rw 0x0 Enable GEM1
MID_GEM0 14 rw 0x0 Enable GEM0
MID_QSPI 13 rw 0x0 Enable QSPI
MID_NAND 12 rw 0x0 Enable NAND
MID_SD1 11 rw 0x0 Enable SD1
MID_SD0 10 rw 0x0 Enable SD0
MID_LPD_DMA[6:7] 9 rw 0x0 Enable LPD DMA [ch 6:7]
MID_LPD_DMA[4:5] 8 rw 0x0 Enable LPD DMA [ch4:5]
MID_LPD_DMA[2:3] 7 rw 0x0 Enable LPD DMA [ch 2:3]
MID_LPD_DMA[0:1] 6 rw 0x0 Enable LPD DMA [ch 0:1]
MID_DAP_APB 5 rw 0x0 Enable Debug Access Port APB
MID_USB1 4 rw 0x0 Enable USB1
MID_USB0 3 rw 0x0 Enable USB0
MID_PMU 2 rw 0x1 Enable PMU
MID_RPU1 1 rw 0x0 Enable RPU1
MID_RPU0 0 rw 0x0 Enable RPU0