Secure PL Peripherals

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

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1.1 English

The S_AXI_XMPU configuration port of the XMPU_PL will be designated as secure, which means that it will only be accessible by the Secure masters, PMU and RPU (R5_0). If you use the LOCK registers in the XMPU, the configuration port becomes writable to only the designated masters, but still is readable by other masters.