Connecting Directly to PS Master I/Fs

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

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1.1 English

The following figure shows the S_AXI port of the XMPU_PL may be directly connected to a PS master I/F. The data widths of both interfaces are selectable in their respective IP customization settings in the IP integrator. It is the responsibility of the user to ascertain that both are set to the same value.

Figure 1. PS Master I/F Direct Connection
Note: The XMPU_PL will not provide any AXI data width conversion. Use SmartConnect upstream, and/or AXI-Interconnect downstream, to provide any needed data or clock conversions between the PS Master and end-point PL-Slaves.