The zupl_xmpu_v1_0 bridges PL and PS security and isolation for AXI based embedded designs in Zynq UltraScale+ devices. The following appendix provides the Master ID list and SW driver details.
The zupl_xmpu_v1_0 bridges PL and PS security and isolation for AXI based embedded designs in Zynq UltraScale+ devices. The following appendix provides the Master ID list and SW driver details.