IDS Interrupt Disable Register

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

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1.1 English

The IDS register is shown in the following table.

  • 0: no effect.
  • 1: disable interrupt (sets mask = 1). Write-only.
Table 1. IDS (XMPU_PL) Register Bit Field Summary
Field Name Bits Type Reset Value Description
Reserved 31:4 ro 0x0 Reserved
SecurityVIO 3 wo 0x0 Security violation by AXI Master
WrPermVIO 2 wo 0x0 Write Permission violation
RdPermVIO 1 wo 0x0 Read Permission violation
Reserved 0 wo 0x0 Reserved