Non-Secure Shared Memory & Peripherals

The middle two KBs of the PL BRAM and the AXI GPIO are designated as non-secure shared. They must be accessible by both secure and non-secure masters. One way to accomplish this is to designate regions to cover their respective address ranges and list all the masters as authorized. Alternatively, omit defining a region and instead utilize the default CTRL register settings to allow read and write access to undefined ranges.

The following table shows the XMPU_PL configuration for the example design. The MACRO definitions can be found in the zupl_xmpu BSP SW driver (zupl_xmpu_hw.h).