Rxx_END Region Ending Address Register

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

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1.1 English

The R[n]_END register is shown in the following table. Each region is defined by a start and end address base addresses mapped to the PL.

Note: Address Offset: 0x00000[n]04
Table 1. R[n]_END (XMPU_PL) Register Bit Field Summary
Field name Bits Type Reset Value Description
ADDR 31:0 rw 0x0

AXI address within the PL.

Note: Bits [31:0] correspond to address bits [39:8].