System Isolation

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

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1.1 English

The isolation reference design created in Isolation Methods in Zynq UltraScale+ MPSoCs (XAPP1320) is the starting point for building the PL isolation example design. The TrustZone (TZ) settings for the Processing System (PS) are shown in the following figure.

Figure 1. Isolation Reference Design TrustZone Settings

The system contains three active PS masters. The PMU and RPU (r5_0) are designated Secure, and the APU is designated Non-Secure. All three masters execute as bare metal standalone OS.

The PL isolation example design adds the PL memory and peripheral elements shown in the following figure.

Figure 2. PL Isolation Security Settings