Error Status 2 Register

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

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1.1 English

The ERR_STATUS2 register is shown in the following table. The first AXI violation is recorded. Once an ISR[3:1] status bit is set, subsequent violations are not recorded, but their transactions are poisoned. The status bits are cleared by a system reset and can be cleared by a software.

Table 1. ERR_STATUS2 (XMPU_PL) Register Bit Field Summary
Field Name Bits Type Reset Value Description
Reserved 31:10 ro 0x0


AXI_ID 9:0 ro 0x0

Master ID from a poisoned read or write transaction. Read-only.