LOCK Register

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

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1.1 English

The LOCK register is shown in the following table.

Register writes to ZUP_XMPU_PL may be done by any bus masters when LOCK [RegWrDis] = 0. When LOCK [RegWrDis] = 1, all register writes may only be done by secure bus masters enabled in LOCK_BYPASS register. The write lock prevents all other masters from writing to all registers except the interrupt status registers: ISR, IMR, IEN and IDS.

Note: All ZUP_XMPU_PL registers are readable by secure or non-secure bus masters.
Note: Regardless of the LOCK [RegWrDis] setting, the status registers are always writable by secure and non-secure bus masters.
Table 1. LOCK (XMPU_PL) Register Bit Field Summary
Field Name Bits Type Reset Value Description
RegWrDis 0 rw 0x0

Register Write Disable. Applies to all registers except ISR, IMR, IEN and IDS.

0: read/write allowed

1: read-only

Once this bit is set, it can only be cleared by a master enabled in the LOCK_BYPASS register.