Manual Insertion of the XMPU_PL in the IP Integrator - XAPP1353

1. Click the Address Editor and note the current mappings in the following pane.
   1. axi_bram_ctrl_0 is mapped to 0x00_A000_0000 (4K) and axi_gpio_0 is mapped to 0x00_A000_1000 (4K) in the Address Editor window. Return to the diagram.
   Figure 1. Address Editor
2. Add the zupl_xmpu_v1_0 core to your repository.
   1. Click Settings beneath Project Manager. This is located in the Flow Manager.
   2. Under Project Settings, expand > IP, and click Repository.
   3. Click the + symbol in the IP Repositories.
   4. Browse to the zupl_xmpu_v1_0 directory and click Select.
   5. One (1) repositiory must be added to the project. Click OK to clear the Add Repository window.
   6. Click OK to clear the Settings window.
3. Add the zupl_xmpu_v1_0 core to the block design.
   1. Click the + symbol in the Block Diagram window.
   2. Type zupl in the Search field type and double-click zupl_xmpu_v1_0 or press enter.
4. Add a SmartConnect IP core.
   1. Click the + symbol in the Block Diagram window.
   2. Type smart in the search field type.
   3. Double-click AXI SmartConnect or just press enter.
   4. Right-click the smartconnect_0 instance and select Customize Block.
   5. Change the Number of Master Interfaces to 2 and click OK.
5. Disconnect the AXI Interconnect block from the Zynqzynq PS block.
   1. Select and delete the bus signals between zynq_ultra_ps_e_0 and ps8_0_axi_periph.
   2. Right-click ps8_0_axi_periph and Customize Block.
   3. Reduce the Number of Slave Interfaces to 1. Click OK.
6. Connect the Zynq PS M_AXI_ ports.
   1. Connect zynq_ultra_ps_e_0/M_AXI_HPM0_FPD to smartconnect_0/S00_AXI.
   2. Connect zynq_ultra_ps_e_0/M_AXI_HPM1_FPD to smartconnect_0/S01_AXI.
7. Connect the XMPU AXI ports.
   1. Connect zupl_xmpu_0/S_AXI_XMPU to smartconnect_0/M00_AXI.
   2. Connect zupl_xmpu_0/S_AXI to smartconnect_0/M01_AXI.
   3. Connect zupl_xmpu_0/M_AXI to ps8_0_axi_periph/S00_AXI.
   4. Regenerate Layout. Click OK.
8. Connect the AXI clock and reset ports.
   1. Click Run Connection Automation.
   2. Select All Automation. Click the Regenerate button.
      
   3. Manually connect any unconnected aclk or aresetn ports.
9. Connect the IRQ signal.
   1. This example design demonstrates the usage of PMU and RPU to receive interrupts from the XMPU so the pmu_error_from_pl port needs to be enabled. Right-click zynq_ultra_ps_e_0 and select Customize Block.
   2. Click PS-PL Configuration. Expand > General. Expand > Others.
   3. Select the check box for Errors to and from PMU. Click OK.
   4. Connect zupl_xmpu_0/irq port to both pl_ps_irq0[0:0] and pmu_error_from_pl[3:0] ports on zynq_ultra_ps_e_0.
   5. Regenerate Layout. The diagram resembles the following.
      Figure 2. xmpu_pl Example Block Diagram
10. Map the Address segments.
    1. Click Address Editor.
    2. Assign addresses:
       1. Expand > Network 0 > zynq_ultra_ps_e_0 > Data > Unassigned (4).
       2. Right-click zupl_xmpu_0: S_AXI_XMPU (S_AXI_XMPU_Config) and select Assign.
          Note: If two entries are shown, select either one.
       3. Change the range of S_AXI_XMPU to 4K.
       4. Change the Master Base Address of S_AXI_XMPU to 0x00_A000_2000.
       5. Select File > Save Block Design.
       6. Select Tools > Validate Design.
          Note: If asked to assign unmapped slaves, select No.
       7. Ignore warnings about unmapped slaves. Click OK.
       8. Right-click Uassigned Slaves/zupl_xmpu_0: S_AXI (S_AXI) and select Exclude.
       9. The final configuration is shown in the following diagram.
          Figure 3. xmpu_pl Example Address Map
       10. Select File > Save Block Design.
    Note: The zupl_xmpu_0/S_AXI is excluded due to the AXI Bridge in the core. Downstream slaves are mapped directly to upstream masters.
11. Customize the zupl_xmpu_0 block.
    1. Return to the block diagram and right-click zupl_xmpu_0 and select Customize Block.
    2. Select AXI Settings.
    3. The C_S_AXI_ DATA_WIDTH is set to the default value of 32. Leave it at default setting. The AXI infrastructure blocks adjusts for the PS M_AXI_ bus widths.
    4. The M_AXI_BASEADDR and M_AXI_HIGHADDR will not have any functional effect. However they are provided as a means to communicate to the SW Driver the address range that the XMPU monitors. These values will be exported to the xparameters.h file and be included in the peripheral's instance configuration data.
    5. (Optional) Set these values to correspond with the address ranges shown in the previous figure.
       1. HIGHADDR:0xA0001FFF
       2. BASEADDR:0xA0000000
          Tip: Use the upper 32 bits to specify a 40 bit address..
    6. Select the Regions Tab and note the value for Regions Max. The default is the absolute maximum setting at 16. If the HW designer knows exactly how many regions the SW designer needs, they could select a lower number to conserve the PL resources. The setting can be kept to default for the time being.
    7. Click OK.
12. (Optional) Set Project Synthesis Language.
    1. The top level synthesis language for the project may optionally be set to either VHDL or Verilog. You can choose either one of them for this demonstration.
    2. Click Settings in the Flow Manager under Project Settings.
    3. Click General under Project Settings.
    4. Select the Target Language: VHDL or Verilog. Click OK.
13. Create the top level wrapper.
    1. In the Sources window, right-click Base_Zynq_MPSoC and select Create HDL Wrapper.
    2. Let Vivado manage wrapper. Click OK.
14. Implement design.
    1. Click Generate Block Design under IP Integrator.
       1. Select Out of context per IP and click Generate.
    2. If a Generate Output Products dialogue appears when the module runs have launched:
       1. Click OK.
    3. Wait for all the block runs to complete.
       1. View the status in the upper right corner or monitor the Out-of-Context Module Runs on the Design Runs tab below.
    4. Click Generate Bitstream in the Flow Navigator, click OK or Yes and then OK.
    5. When the Bitstream Generation Completed window appears, click Cancel.
15. Export hardware.
    1. Select File->Export->Export Hardware.
       1. Check Include bitstream.
    2. Click Next.
       1. XSA file name: Base_Zynq_MPSoC_wrapper
       2. Export to:

           <your_path>/XmpuPL_ZUplus_v1.0a/zcu102_<version>/xmpu_example/pl_isolation_lab.vitis/Base_Zynq_MPSoC_wrapper_hw_platform

          If prompted, click OK to Create Directory.
          Figure 4. Export Hardware in Vitis
       3. Click OK or Next > then Finish.

The hardware design is now complete. Proceed to Creating the Isolation Test SW Applications in Vitis 2021.1.