Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

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1.1 English

Isolation design methods help protect the system from erroneous application software and misbehaving hardware interfaces. Erroneous software may include malicious or unintentional code behavior that may corrupt system memory or cause system failures. Misbehaving hardware includes incorrect device configuration, malicious functionality, or unintentional design. The AMD Zynq™ AMD UltraScale+™ devices includes TrustZone (TZ) technology to facilitate system design isolation.

The Zynq UltraScale+ MPSoCs and Zynq UltraScale+ RFSoCs incorporate many features for design security that includes Arm® TrustZone (TZ) technology, AMD peripheral protection units (XPPU), AMD memory protection units (XMPU), a system memory management unit (SMMU), AXI translation buffer units (TBU), and TZ control registers for protection within the PS AXI infrastructure.

For more information, on TrustZone, Security, and Anti-Tamper measures, refer to the Zynq UltraScale+ Device Technical Reference Manual (UG1085). Isolation Methods in Zynq UltraScale+ MPSoCs (XAPP1320) provides a detailed example of implementing design isolation for the PS sub-systems.

This application note extends the isolation methods, described in XAPP1320, into the programmable Logic (PL) sub-system of the example design, by introducing a VHDL based XMPU PL softcore, to bridge the gap between PS and PL isolation methods including PS-to-PL interfaces.

Note: It is strongly recommended that you complete the isolation design tutorial in Isolation Methods in Zynq UltraScale+ MPSoCs (XAPP1320) prior to proceeding with the tutorials in this document. While the reference design in this application note specifically targets Zynq UltraScale+ MPSoC, all isolation methods apply to the Zynq UltraScale+ devices as well.