Reference Design

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

Document ID
Release Date
1.1 English

Download the reference design files for this application note from the AMD website.

Reference Design Matrix

The following checklist indicates the procedures used for the provided reference design.

Table 1. Reference Design Matrix
Parameter Description
Developer name Carl Carmichael
Target devices Zynq UltraScale+ Devices
Source code provided? Yes
Source code format (if provided) C, VHDL
Design uses code or IP from existing reference design, application note, 3rd party or Vivado software? If yes, list. Isolation Methods in Zynq UltraScale+ MPSoCs (XAPP1320)
Functional simulation performed Yes
Timing simulation performed? No
Test bench provided for functional and timing simulation? No
Test bench format No
Simulator software and version Yes
SPICE/IBIS simulations N/A
Synthesis software tools/versions used N/A
Implementation software tool(s) and version N/A
Static timing analysis performed? Yes
Hardware Verification
Hardware verified? Yes
Platform used for verification ZCU102 Evaluation Board