Master IDs

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

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1.1 English

Each XMPU_PL Region and Lock_Bypass monitors use the Master ID in each AXI transaction to validate the transaction. The REGION MASTERS register selects specific Masters. Refer to the Functional Description section for a detailed register description. All the Master IDs and associated Masks are stored in the zupl_xmpu reference design vhdl package. The Master ID is masked by a [MIDM] bit field and then compared against a [MID] bit field.

Depending on AXI Security Permission checks, the transaction is allowed when the following equation is satisfied:

[MID] and [MIDM] == AXI_MasterID and [MIDM]

For more information on Master ID, refer to the Zynq UltraScale+ Device Technical Reference Manual (UG1085). There are fifty masters with unique IDs in the Zynq UltraScale+ MPSoCs. These are summarized in the Appendix A: Master ID List.

Note: The user need not know the specific MasterID values to configure the XMPU_PL Region and Lock_Bypass. As described in the Functional Description section, each bit position within those registers corresponds to a particular master (master-pairs for DMA channels) that are enabled or disabled.