The QSFP-DD control signals can be asserted in multiple ways. Each QSFP-DD has an I2C connection to the I2C1 bus through the I2C multiplexer (TCA9548PWR U35) as shown in the PMC MIO[44:45] I2C1 Bus section.
The following table lists the QSFP-DD control signals.
| Signal Name | Feature | Notes | Schematic Page |
|---|---|---|---|
| QSFPDD1_MODSELL | Module select | U1 V34, U233 P02 | 7, 45, 50 |
| QSFPDD1_RESETL | Module reset | U1 V35 | 7, 45 |
| QSFPDD1_MODPRSL | Module present | U1 R31 | 7, 45 |
| QSFPDD1_INTL | Interrupt | U1 T31 | 7, 45 |
| QSFPDD1_INITMODE | Low power mode | U1 P37 | 7, 45 |
| QSFPDD_I2C_SDA | Two-wire interface data | U35 I2C MUX | 43, 45 |
| QSFPDD_I2C_SCL | Two-wire interface clock | U35 I2C MUX | 43, 45 |
| QSFPDD2_MODSELL | Module select | U1 R37, U233 P03 | 7, 45 , 50 |
| QSFPDD2_RESETL | Module reset | U1 P33 | 7, 45 |
| QSFPDD2_MODPRSL | Module present | U1 R31 | 7, 45 |
| QSFPDD2_INTL | Interrupt | U1 T31 | 7, 45 |
| QSFPDD2_INITMODE | Low power mode | U1 T36 | 7, 45 |