[Figure 1, callout 17]
The detailed ACAP connections for the feature described in this section are documented in the VPK120 board XDC file, referenced in Xilinx Design Constraints.
[Figure 1, callout 17]
The detailed ACAP connections for the feature described in this section are documented in the VPK120 board XDC file, referenced in Xilinx Design Constraints.