The XCVP1202 ACAP PL I/O bank voltages on the
VPK120 board are listed in the following table. See LPD MIO[23]: VADJ_FMC Power Rail for more details on the VADJ_FMC power rail.
Note: The VPK120 evaluation board is
shipped with VCC_PMC set to 0.88V, allowing for overdrive. See the
Versal Premium Series Data Sheet: DC and AC Switching
Characteristics (DS959) for more information. See the
Versal
ACAP Technical Reference Manual (AM011) for more information about
Versal ACAP configuration
options.
| ACAP (U1) Bank | Power Supply Rail Net Name | Voltage | Description |
|---|---|---|---|
| XPIO Bank 700 | VCC1V1_LP4 | 1.1V | LPDDR4 TRIP1 CH1 |
| XPIO Bank 701 | VCC1V1_LP4 | 1.1V | LPDDR4 TRIP1 CH0, LPDDR4 TRIP1 CH1 |
| XPIO Bank 702 | VCC1V1_LP4 | 1.1V | LPDDR4 TRIP1 CH0 |
| XPIO Bank 703 | VCC1V1_LP4 | 1.1V | LPDDR4 TRIP2 CH1 |
| XPIO Bank 704 | VCC1V1_LP4 | 1.1V | LPDDR4 TRIP2 CH0, LPDDR4 TRIP2 CH1 |
| XPIO Bank 705 | VCC1V1_LP4 | 1.1V | LPDDR4 TRIP2 CH0 |
| XPIO Bank 706 | VCC1V1_LP4 | 1.1V | LPDDR4 TRIP3 CH1 |
| XPIO Bank 707 | VCC1V1_LP4 | 1.1V | LPDDR4 TRIP3 CH0, LPDDR4 TRIP3 CH1 |
| XPIO Bank 708 | VCC1V1_LP4 | 1.1V | LPDDR4 TRIP3 CH0 |
| XPIO Bank 709 | VADJ_FMC 1 | 1.5V (default) | FMCP1_LA[17:18]_CC,FMCP1_LA[19:33], FMCP1_SYNC, FMCP_CLK1 |
| XPIO Bank 710 | VADJ_FMC 1 | 1.5V (default) | FMCP1_LA[00:01]_CC, FMCP1_LA[02:16], FMCP1_CLK0 |
| XPIO Bank 711 | VCC1V5 | 1.5V | 8A34001_GPIO_[0:15], SYSCTLR_GPIO[0:15], 8A34001_Q6_OUT |
| XPIO Bank 712 | VCC1V5 | 1.5V | GPIO_PB[0:1], GPIO_DIP_SW[0:3], GPIO_LED_[0:3]_LS, UART1, QSFPDD1/2 control signals, TRACE signals |
| PMC MIO 500 | VCCO_MIO | 1.8V | SYSMON, USB ULPI 2.0 interface, QSPI1/2 interface |
| PMC MIO 501 | VCCO_MIO | 1.8V | SD bus power, PCIe controls, I2C0/21, UART0, Sys Controller I2C/trigger, SD card controls, GEM reset |
| LPD MIO 502 | VCCO_502 | 1.8V | GEM interface/controls, power enables, PCIe PERST, fan tach, fan PWM |
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