[Figure 1, callout 2, 3, 4]
The VPK120 XCVP1202 ACAP PL DDR memory interface performance is documented in the Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959). The VPK120 board LPDDR4 component memory interfaces adhere to the constraints guidelines documented in the "PCB guidelines for Memory Interfaces" section of the Versal ACAP PCB Design User Guide (UG863). The VPK120 DDR4 component interface is a 40Ω impedance implementation. Other memory interface details are also available in the Versal ACAP Memory Resources Architecture Manual (AM007). For more memory component details, see the Micron MT53D512M32D2DS data sheet on the Micron website. For the most current part number, see the Bill of Materials (BOM) located on the VPK120 Evaluation Board website. The detailed ACAP connections for the feature described in this section are documented in the VPK120 board XDC file, referenced in Xilinx Design Constraints.
The VPK120 evaluation board hosts three LPDDR4 memory systems, each with a component configuration of 2x (1x32-bit component).
XCVP1202 U1 has been configured with three triplet banks.
- XPIO triplet 1 (banks 700/701/702)
- XPIO triplet 2 (banks 703/704/705)
- XPIO triplet 3 (banks 706/707/708)
Each support two independent 32-bit 2 GB component interfaces (4 GB per triplet). The VPK120 evaluation board uses the LPDDR4 memory components as follows:
- Manufacturer: Micron
- Part number: MT53D512M32D2DS-046 WT:D (dual die LPDDR4 SRAM)
- Component description
- 16 Gb (512 Mb x 32)
- 1.1V 200-ball WFBGA
- DDR4-2133
The VPK120 XCVP1202 ACAP PL DDR interface performance is documented in the Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959). The VPK120 evaluation board LPDDR4 component memory interfaces adhere to the constraints guidelines documented in the PCB guidelines for the DDR4 section of the Versal ACAP PCB Design User Guide (UG863). The VPK120 DDR4 component interface is a 40Ω impedance implementation. Other memory interface details are also available in the Versal ACAP Memory Resources Architecture Manual (AM007). For more memory component details, see the Micron MT53D512M32D2DS data sheet at the Micron website. The detailed ACAP connections for the feature described in this section are documented in the VPK120 evaluation board XDC file, referenced in Xilinx Design Constraints.