[Figure 1, callout 11]
The VPK120 evaluation board includes a secure digital input/output (SDIO) interface to provide access to general purpose non-volatile SDIO memory cards and peripherals. This interface is used for the SD boot mode and supports SD2.0 and SD3.0 access.
The SDIO interface signals PMC_MIO[26:36, 51] are connected to XCVP1202 ACAP bank 501, which has its VCCO set to 1.8V. Six SD interface nets PMC_MIO[26, 29, 30:33] are passed through a NXP NVT4857UK SD 3.0-compliant voltage level-translator U104. This translator is present between the Versal ACAP and the SD card connector (J302). The NXP NVT4857UK U104 device provides SD3.0 capability with SDR104 performance. The following figure shows the connections of the SD card interface on the VPK120 evaluation board.
The following table lists the NVT4857UK U104 adapter pinout.
| Aries Adapter Pin Number | NVT4857UKAZ Pin Number | NVT4857UKAZ Pin Name |
|---|---|---|
| 1 | D2 | CLKA |
| 2 | C3, C2 | GND |
| 3 | B2 | CD |
| 4 | C1 | CMDA |
| 5 | E2 | CLK_FB |
| 6 | Unused | Unused |
| 7 | B3 | VCCB |
| 8 | Unused | Unused |
| 9 | Unused | Unused |
| 10 | A3 | VSD |
| 11 | A2 | VCCA |
| 12 | Unused | Unused |
| 13 | D1 | DATA0 |
| 14 | E3 | SEL |
| 15 | B1 | DAT3A |
| 16 | E1 | DAT1A |
| 17 | Unused | Unused |
| 18 | A1 | DAT2A |
| 19 | E4 | DAT1B |
| 20 | D4 | DAT0B |
| 21 | D3 | CLKB |
| 22 | C4 | CMDB |
| 23 | B4 | DAT3B |
| 24 | A4 | DAT2B |
| 25 | Unused | Unused |
The ACAP (U1) also has control over the power for the SDCARD, which allows the ACAP to remove power to the SD card as needed.
Information for the SD I/O card specification can be found at the SanDisk Corporation or SD Association websites. The VPK120 SD card interface supports the SD1 (2.0) and SD2 (3.0) configuration boot modes documented in the Versal ACAP Technical Reference Manual (AM011). See schematic page 39 for more details.
For NVP NVT4857UK component details, see the NVT4857UK data sheet on the NXP website.
The detailed ACAP connections for the feature described in this section are documented in the VPK120 board XDC file, referenced in Xilinx Design Constraints.