The VPK120 board provides fixed and variable clock sources for the XCVC1202 U1 adaptive SoC and other function blocks. The following table lists the source devices for each clock.
| Ref. Des. | Feature | Notes | Schematic Page |
|---|---|---|---|
| U248 | LPDDR4 CLK, 200 MHz, 3.3V LVDS, 0x60
|
Skyworks/Silicon Labs 570BAB000299DG | 3 |
| U3 | LPDDR4 CLK, 200 MHz, 3.3V LVDS, 0x60
|
Skyworks/Silicon Labs 570BAB000299DG | 4 |
| U4 | LPDDR4 CLK, 200 MHz, 3.3V LVDS, 0x60
|
Skyworks/Silicon Labs 570BAB000299DG | 5 |
| U32 | Adaptive SoC U1 REF CLK, 33.33 MHz, 1.8V CMOS, 0x5D
|
Skyworks/Silicon Labs 570JAC000900DGR | 42 |
| U205 | Adaptive SoC U1 GTYP CLK, 100 MHz, 3.3V LVDS, 0x5F
|
Skyworks/Silicon Labs 570BAB002038DGR | 46 |
| U219 | IEEE-1588 eCPRI CLK, various, 3.3V, 0x5B
|
Renesas / IDT 8A34001E-000AJG8 | 90 |
The detailed adaptive SoC connections for the feature described in this section are documented in the VPK120 board XDC file, referenced in Xilinx Design Constraints.