Clock Generation

VPK120 Evaluation Board User Guide (UG1568)

Document ID

UG1568

Release Date

2022-08-24

Revision

1.1 English

The VPK120 board provides fixed and variable clock sources for the XCVC1202 U1 ACAP and other function blocks. The following table lists the source devices for each clock.

Table 1. Clock Sources
Ref. Des.	Feature	Notes	Schematic Page
U248	DDR4 DIMM CLK, 200 MHz, 3.3V LVDS, `0x60`	Skyworks/Silicon Labs 570BAB000299DG	3
U3	DDR4 DIMM CLK, 200 MHz, 3.3V LVDS, `0x60`	Skyworks/Silicon Labs 570BAB000299DG	4
U4	DDR4 DIMM CLK, 200 MHz, 3.3V LVDS, `0x60`	Skyworks/Silicon Labs 570BAB000299DG	5
U32	ACAP U1 REF CLK, 33.33 MHz, 1.8V CMOS, `0x5D`	Skyworks/Silicon Labs 570JAC000900DGR	42
U205	ACAP U1 GTYP CLK, 100 MHz, 3.3V LVDS, `0x5F`	Skyworks/Silicon Labs 570BAB002038DGR	46
U219	IEEE-1588 eCPRI CLK, various, 3.3V, `0x5B`	Renesas / IDT 8A34001E-000AJG8	90

The detailed ACAP connections for the feature described in this section are documented in the VPK120 board XDC file, referenced in Xilinx Design Constraints.