Board Features

The VPK120 evaluation board features are listed here. Detailed information for each feature is provided in Board Component Descriptions.

• XCVP1202, VSVA2785 package
• Form factor: extended height PCIe® , double-slot (heatsink clearance)
• Onboard configuration from:
  • USB-to-JTAG bridge
  • JTAG pod 2 mm 2x7 flat cable connector
  • microSD card (PS MIO I/F)
  • Quad SPI (QSPI)/eMMC (system controller I/F)
  • Dual QSPI
• Clocks
  • ACAP bank 702/5/8 Si570 LPDDR4_CLK1/2/3 (DIMM) 200 MHz
  • ACAP bank 503 Si570 REF_CLK 33.3333 MHz
  • ACAP bank GTY200/1 (REFCLK0) FMC_SI570_BUF0/1 100 MHz
  • IEEE-1588 eCPRI 8A34001 clocks (various)
  • ACAP bank 503 RTC Xtal 32.768 kHz
  • ACAP bank GTY102/3/4/5 (REFCLK0) PCIe_CLK3/2/1/0 (from card edge)
  • ACAP bank GTY200/1 (REFCLK0) FMC_SI570_BUF0/1 100 MHz
  • ACAP bank GTY200/1 (REFCLK1) FMC_SI570_BUF0/1 100 MHz
• Three LPDDR4 interfaces (2x32-bit 4 GB components each)
  • XPIO triplet 1 (banks 700, 701, 702)
  • XPIO triplet 2 (banks 703, 704, 705)
  • XPIO triplet 3 (banks 706, 707, 708)
• PL FMCP HSPC (FMC+) connectivity
  • FMCP1 HSPC full LA[00:33] bus
• PL GPIO connections
  • PL UART1 to FTDI
  • PL GPIO DIP switch (4-position)
  • PL GPIO LEDs (four)
  • PL GPIO pushbuttons (two)
  • PL trace connector (J332)
  • PL SYSCTLR_GPIO[0:15]
  • PL 8A34001_GPIO[0:15]
• 28 GTYP transceivers (7 quads)
  • PCIe 16-lane edge connector (16, banks GTYP102 - GTYP105)
  • FMCP1 HSPC DP (8, banks GTYP200, GTYP201)
  • Not used (4, bank GTYP106)
• 20 PL GTM transceivers (5 quads)
  • QSFPDD1 (8, banks GTM204, GTM205)
  • QSFPDD2 (8, banks GTM202, GTM203)
  • User SMA connectors (1, bank GTM206)
• PCI Express endpoint connectivity
  • 16-lane (banks GTY102 - GTY105)
• PS PMC MIO connectivity
  • PS MIO[0:12]: boot configuration QSPI
    • DC QSPI support
  • PS MIO[13:25]: USB2.0
  • PS MIO[26:36, 51]: SD1 I/F
  • PS MIO[37]: ZU4_TRIGGER
  • PS MIO[38]: PCIe_PWRBRK
  • PS MIO[39:41]: SYSMON_I2C
  • PS MIO[42:43]: UART0 to FTDI
  • PS MIO[44:47]: I2C1, I2C0
  • PS MIO[48], PS LPD MIO[0:11, 24:25]: GEM0 RGMII Ethernet RJ-45
  • PS MIO[49] and LPD MIO[13,15:16,20]: power enable
  • PS MIO[50] and LPD MIO[18:19]: PCIe status
  • PS LPD MIO [21:22]: optional fan interface
  • LPD MIO[23]: VADJ_FMC power rail
• Security: PSBATT button battery backup
• SYSMON header
• Operational switches (power on/off, PROG_B, boot mode DIP switch)
• Operational status LEDs (INIT, DONE, PS STATUS, PGOOD)
  • See Power and Status LEDs
• Power management
• System controller (XCZU4EG)

The VPK120 evaluation board provides a rapid prototyping platform using the XCVP1202-2MSEVSVA2785 device. See the Versal Architecture and Product Data Sheet: Overview (DS950) for a feature set overview, description, and ordering information.