Ethernet PHY LED Interface

VPK120 Evaluation Board User Guide (UG1568)

Document ID
UG1568
Release Date
2022-08-24
Revision
1.1 English

[Figure 1, callout 16]

Each DP83867 PHY (GEM0 U198) controls two LEDs in the J307 two port connector bezel. The PHY signal LED0 drives the green LED, and LED1 drives the yellow LED. The LED2 signal is not used.

The LED functional description is listed in the following table.

Table 1. Ethernet PHY LED Functional Description
DP83867IS PHY Pin Type Description
Name Number
LED_2 45 S, I/O, PD By default, this pin indicates receive or transmit activity. Additional functionality is configurable using LEDCR1[11:8] register bits.
LED_1 46 S, I/O, PD By default, this pin indicates that 100BASE-T link is established. Additional functionality is configurable using LEDCR1[7:4] register bits.
LED_0 47 S, I/O, PD By default, this pin indicates that link is established. Additional functionality is configurable using LEDCR1[3:0] register bits.

The LED functions can be repurposed with a LEDCR1 register write available via the PHY's management data interface, MDIO/MDC.

See the TI DP83867 RGMII PHY data sheet at the Texas Instruments website for component details.

The detailed ACAP connections for the feature described in this section are documented in the VPK120 board XDC file, referenced in Xilinx Design Constraints.