[Figure 1, callout 35]
The VPK120 evaluation board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator (U205) driving 8P34S1102NLGI (U249) 1-to-2 clock buffer input. The clock buffer generates two copies of the input clock. The FMC_SI570_BUF0_C_P/N and FMC_SI570_BUF1_C_P/N series capacitor coupled clock signals are connected to XCVP1202 ACAP U1 bank 200 and bank 201, respectively.
At power-up, SI570 (U205) defaults to an output frequency of 100.000 MHz. User applications or the system controller can change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the VPK120 board reverts this user clock to the default frequency of 100.000 MHz.
- Programmable oscillator: Skyworks/Silicon Labs SI570BAB002038DG
- 10 MHz-945 MHz range, 100.000 MHz default
- I2C address
0x5F - LVDS differential output, total stability: 61.5 ppm