PMC MIO[44:45] I2C1 Bus

VPK120 Evaluation Board User Guide (UG1568)

Document ID
Release Date
1.1 English

[Figure 1, callout 12]

Bus I2C1 connects the XCVP1202 U1 PS bank 501, and the XCZU4EG system controller U125 PS bank 501 to one I2C switch (TCA9548A U35). These I2C1 connections enable I2C communications with other I2C capable target devices. TCA9548A U35 is pin-strapped to respond to I2C address 0x74. The following figure shows the I2C1 bus connectivity detailed in the table below.

Details for controlling the U35 TCA9548A switch are available in the data sheet on the Texas Instruments website.

The detailed ACAP connections for the feature described in this section are documented in the VPK120 evaluation board XDC file, referenced in Xilinx Design Constraints.

Figure 1. I2C1 Bus Topology

U34 is an I2C addressable 128-Kbit serial I2C bus EEPROM. It has two addresses associated with it and is connected at the same I2C level as the I2C multiplexer listed in the following table. Address 0x54 is used when the memory array is accessed. When using 0x5C, the identification page is accessed.

The U35 address 0x74 connections are listed in the following table.

Table 1. I2C1 Multiplexer TCA9548A U35 Address 0x74 Connections
I2C Devices I2C MUX Pos. I2C Address Devices
REF_CLK_I2C 0 0x5D U32
FMCP1_IIC 1 0x## J51
No connect 2 N/A
LPDDR4_SI570_CLK3 3 0x60 U4
LPDDR4_SI570_CLK2 4 0x60 U3
LPDDR4_SI570_CLK1 5 0x60 U248
QSFPDD_I2C 6 0x## J1, J2
8A34001 7 0x5B U219, J310