The Vivado® , Xilinx SDK, or third-party tools can establish a JTAG connection to the Versal ACAP in the two ways described in this section.
- FTDI FT4232 USB-to-JTAG/USB-UART device (U20) connected to USB 2.0
type-A micro connector (J344), which requires:
- Set boot mode SW1 for JTAG as indicated in the "Mode Switch SW1 Configuration Option Settings" table in Versal ACAP Configuration.
- Set 2-pole DIP SW3[1:2] set to 01 (ON, OFF) for JTAG MUX channel 2 FT4232 U20 bridge.
- On the 3-pin JTAG MUX, enable header J37 to enable the JTAG MUX. Move the 2-pin jumper to be installed on pins 2-3. See Default Jumper and Switch Settings for defaults and Board Component Location for location.
- Power-cycle the VPK120 evaluation board or press the power-on reset (POR) pushbutton (SW2). SW2 is near the mode pin dip switch in the figure in Board Component Location).
- JTAG pod flat cable connector J36 (2 mm 2x7 shrouded/keyed), which
requires:
- Set boot mode SW1 for JTAG as indicated in the "Mode Switch SW1 Configuration Option Settings" table in Versal ACAP Configuration.
- On the 3-pin JTAG MUX, enable header J37 to inhibit the JTAG MUX. Move the 2-pin jumper to be installed on pins 1-2 for high-z mode. See Default Jumper and Switch Settings for defaults and Board Component Location for location.
- 2-pole DIP SW3[1:2] setting is XX as the MUX is inhibited/turned off.
- In this mode, the FT4232 device (U20) UART functionality continues to be available.
- Power-cycle the VPK120 board or press the power-on reset pushbutton (SW2). SW2 is near the mode pin dip switch in the figure in Board Component Location).