[Figure 1, callout 47]
The 8A34001 synchronization management unit (SMU) provides tools to manage timing references, clock sources, and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, digitally controlled oscillators (DCO), or digital phase lock loops (DPLL). The following block diagram can aid in quickly determining the overall clock tree for the 8A34001 (U219). See schematic pages 90-91 for details. For more details on programming and controlling the 8A34001, see the Renesas/Integrated Device Technology, Inc. (IDT) website and data sheet.
Figure 1. IEEE-1588 eCPRI Block Diagram
