LPD MIO[23]: VADJ_FMC Power Rail

VPK120 Evaluation Board User Guide (UG1568)

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1.1 English

The VPK120 evaluation board implements the ANSI/VITA 57.4 IPMI support functionality. The power control of the VADJ_FMC power rail is managed by the ZU4 U125 system controller. This rail powers FMCP HSPC J51 VADJ pins, as well as the XCVP1202 U1 VCCO on the FMCP interface banks 709 and 710. The valid values of the VADJ_FMC rail are 0, 1.2V, or 1.5V. At power on, the system controller detects if an FMC module is installed on J51. The Versal ACAP also has control over the active-High enable line on the voltage regulator.

If the Versal ACAP has enabled the voltage regulator (active-High), the following sequence of actions occur:

  • If no card is attached to a FMCP connector, the VADJ_FMC voltage is set to 1.5V
  • When an FMC card is attached, its IIC EEPROM is read to find a VADJ voltage supported by both the VPK120 board and the FMC module, within the available choices of 0, 1.2V, or 1.5V
  • If no valid information is found in an attached FMC card IIC EEPROM, the VADJ_FMC rail is set to 0.0V

The system controller user interface allows the FMC IPMI routine to be overridden and an explicit value can be set for the VADJ_FMC rail. The override mode is useful for FMC mezzanine cards that do not contain valid IPMI EPROM data defined by the ANSI/VITA 57.4 specification.