PMC MIO[42:43] UART0

VPK120 Evaluation Board User Guide (UG1568)

Document ID
Release Date
1.1 English

[Figure 1, callout 9]

This is the primary Versal ACAP PS-side UART interface. MIO42 (RX_IN) and MIO43 (TX_OUT) are connected to FTDI FT4232HL U20 USB-to-Quad-UART bridge port BD through TI SN74AVC4T245 level-shifters U18 and U21. The FT4232HL U20 port assignments are listed in the following table.

Table 1. FT4232HL Port Assignments
FT4232HL U34 Versal ACAP U1
Port AD JTAG VPK120 JTAG chain
Port BD UART0 PS_UART0 (MIO 42-43)
Port CD UART1 PL_UART1 bank 712
Port DD UART2 U20 system controller UART

The FT4232HL UART interface connections are shown in the following figure.

Figure 1. FT4232HL UART Connections

For more information on the FT4232HL, see the Future Technology Devices International Ltd. website.

Note: This FTDI configuration image is not provided nor supported. To replicate this feature, a JTAG-SMT2 from Diligent or similar is recommended.

The detailed ACAP connections for the feature described in this section are documented in the VPK120 board XDC file, referenced in Xilinx Design Constraints.