PMC and LPD MIO

VPK120 Evaluation Board User Guide (UG1568)
Document ID
UG1568
Release Date
2022-08-24
Revision
1.1 English

The following sections provide the MIO peripheral mapping implemented on the VPK120 evaluation board. See the Versal ACAP Technical Reference Manual (AM011) for more information on MIO peripheral mapping. Additional signal connectivity can be located in the following schematic sections:

  • Bank 500: See schematic page 12
  • Bank 501: See schematic page 13
  • Bank 502: See schematic page 13

The following table provides MIO peripheral mapping implemented on the VPK120 evaluation board. The ACAP bank 500, 501, and 502 mappings are listed in the following table.

Table 1. MIO Peripheral Mapping
PMC MIO[0:25] Bank 500 PMC MIO[26:51] Bank 501 LPD MIO[0:25] Bank 502
0 QSPI U12 26 SD1 0 GEM0
1 QSPI U12 27 SD1 1 GEM0
2 QSPI U12 28 SD1 2 GEM0
3 QSPI U12 29 SD1 3 GEM0
4 QSPI U12 30 SD1 4 GEM0
5 QSPI U12 31 SD1 5 GEM0
6 NC 32 SD1 6 GEM0
7 QSPI U11 33 SD1 7 GEM0
8 QSPI U11 34 SD1 8 GEM0
9 QSPI U11 35 SD1 9 GEM0
10 QSPI U11 36 SD1 10 GEM0
11 QSPI U11 37 ZU4_TRIGGER 11 GEM0
12 QSPI U11 38 PCIE_PWRBRK_B 12 NC
13 U103.6 USB3320 U99 reset gate 39 SYSMON I2C 13 VCC_SOC_EN_LS
14 USB3320 U99 40 SYSMON I2C 14 NC
15 USB3320 U99 41 SYSMON I2C 15 VCC_PSFP_EN_LS
16 USB3320 U99 42 UART0 16 VCC1V1_LP4_AUX_EN_LS
17 USB3320 U99 43 UART0 17 NC
18 USB3320 U99 44 I2C1 18 PCIE_PERST_B
19 USB3320 U99 45 I2C1 19 PCIE_PERST_B
20 USB3320 U99 46 I2C0 20 VCC_PL_EN_LS
21 USB3320 U99 47 I2C0 21 Versal fan
22 USB3320 U99 48 GEM0 22 Versal fan
23 USB3320 U99 49 VCC_PSLP_EN 23 VADJ_FMC_EN_LS
24 USB3320 U99 50 PCIE_WAKE_B 24 GEM0
25 USB3320 U99 51 SD1 25 GEM0