Using UltraScale GTH Transceivers for SDI Interfaces

This section supplements the UltraScale Architecture GTH Transceivers User Guide (UG576) and highlights features and operating requirements of the GTH transceivers that are important for UHD-SDI applications.

This application note uses the same naming convention as the UltraScale Architecture GTH Transceivers User Guide (UG576) for the GTH transceiver ports, which uses only the base name of a port. When the AMD UltraScale™ FPGAs Transceiver Wizard is used to create a GTH wizard module, all input ports names have a suffix of _in and all outputs have a suffix of _out. For example, a port named txpllclksel would be txpllclksel_in.

Several clocks are required in applications that use GTH transceivers. The SDI protocol, which does not allow for clock correction by stuffing and removing extra data in the data stream, requires careful attention to how these clocks are generated and used in the application. GTH transceivers require reference clocks to operate. The reference clocks are used by phase-locked loops (PLLs) in the GTH transceiver quad to generate serial clocks for the receiver and transmitter sections of each transceiver. As described in more detail in GTH Transceiver Reference Clocks, the serial bit rate of the GTH transmitter is an integer multiple of the reference clock frequency that it is using. Furthermore, the data rate of the video provided to the input of the SDI transmitter datapath must also exactly match (or be a specific multiple of) the frequency of the reference clock used by the GTH transmitter. Consequently, you must determine how to generate the transmitter reference clock so that it is frequency-locked exactly with the data rate of the video stream being transmitted.

The GTH transmitter clocking is handled by the Transmitter User Clocking Network Helper Block when enabled during GT IP generation from UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182). The txusrclk and txusrclk2 output is driven by a BUFG_GT within the helper block and its frequency is equal to the word rate of the data that must enter the txdata port of the GTH transmitter. The txusrclk and txusrclk2 are generated in the GTH transmitter by dividing the serial clock from the PLL down to the word rate.

The GTH receiver reference clock does not need an exact relationship with the bit rate of the incoming SDI signals. This is because the clock and data recovery (CDR) unit in the GTH receiver can receive bit rates that are up to ±1,250 ppm (≤ 6.6 Gbps) or ±200 ppm (> 8.0 Gbps) away from the nominal bit rate as set by the reference clock frequency. This allows the receiver reference clock to be generated by local oscillators that have no exact frequency relationship to the incoming SDI signal. The GTH receiver generates a recovered clock (rxoutclk) that is frequency-locked to the incoming SDI bit rate. These clocks are output as rxusrclk and rxusrclk2 ports of the Receiver User Clocking Network Helper Block from the GTH Wizard IP and are driven by BUFG_GT. As is described in Generating an SD-SDI Recovered Clock, rxusrclk and rxusrclk2 are true recovered clocks when receiving all SDI line rates except when receiving SD-SDI signals.

One additional clock is required for SDI applications – a free-running, fixed-frequency clock used as the clock for the dynamic reconfiguration port (DRP) of the GTH transceiver. This clock is also usually supplied to the control module in the SDI wrapper for timing purposes. The valid frequency range for this clock is stated in the UltraScale FPGAs Transceiver Wizard and normally ranges from 3.125 to 200 MHz. This clock must not change frequencies when the SDI mode changes. It must remain running at the same nominal frequency at all times and never stop while the SDI application is active. This clock can be used for all SDI interfaces in the device.

The frequency of the rxusrclk and txusrclk depend on the SDI mode and the width of the GTH transceiver's rxdata and txdata ports. This relationship is fixed by the architecture of the GTH transceiver. The receiver and the transmitter both use clock enables to throttle the data stream transfer data rate because, in some cases, the data rate on the data streams is less than the frequency of the clock. The following table shows the relationships between SDI mode, number of active data streams, rxdata/txdata port widths, rxoutclk/txoutclk frequencies, and clock enable cadences. The clock enable cadences are given in number of clocks between assertions of the clock enable over two data word cycles where 1/1 means that the clock enable is asserted every clock cycle, 2/2 indicates assertion every other clock cycle (50% duty cycle), 4/4 indicates assertion every fourth clock cycle (25% duty cycle), and 5/6 indicates that the clock enable alternates between assertion every five or six clock cycles, to average once every 5.5 clock cycles (one instance of five clock cycles between High pulses on the clock enabled followed by one instance of six clock cycles between High pulses on the clock enable, with this pattern repeating).