GTH RX Resets

Implementing SMPTE SDI Interfaces with UltraScale GTH Transceivers Application Note (XAPP1248)

Document ID
XAPP1248
Release Date
2023-11-08
Revision
v1.6 English

As with the TX section, the user application should rely on the SDI control module to carefully coordinate all of the RX reset and dynamic change activities described here to prevent them from interfering with each other. The UltraScale FPGAs Transceiver Wizard offers three ways to reset the RX portion of the GTH Transceiver.

  • gtwiz_reset_all_in: Asserted High. User signal to reset both TX and RX portions of PLLs and active data directions of GTH transceiver. This reset affects TX and RX GTH portions and is thus normally asserted during startup condition.
  • gtwiz_reset_rx_pll_and_datapath_in: Asserted High. User signal to reset the RX data direction and associated PLLs of GTH transceiver. This reset is particularly useful if the reference clock to the RX PLL changes.
  • gtwiz_reset_rx_datapath_in: Asserted High. User signal to reset the RX data direction of transceiver primitives. This reset is asserted for SDI RX application once when at least one of the rx_mode, rx_m, and rx_active_streams ports change.
Note: All the resets mentioned in this application note are asynchronous resets. Refer to the UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182) for more information.

All bit rates (0 ppm and 1000 ppm) from SD-SDI to 6G-SDI can be supported by one CPLL or QPLL because these PLLs offer ±1250 ppm for bit rates ≤ 6.6 Gbps. Conversely, for 12G-SDI, two PLLs (CPLL and one of QPLL or QPLL0 and QPLL1) of GTH transceiver are required to support the two bit rates. This means that for 12G-SDI applications, rxsysclksel must change when switching from 11.88 Gbps to 11.88/1.001 Gbps, and vice versa.

Changes in the SDI mode between SD-SDI, HD-SDI, 3G-SDI, 6G-SDI, and 12G-SDI require changes to one or more of the following:

  • Controlling the rxcdrhold port
  • Enabling or disabling equalization (LPM and DFE)
  • Updating the RXCDR_CFG attribute based on SDI mode
  • RXOUT_DIV, RX_DATA_WIDTH, and RX_INT_DATA_WIDTH attributes.

The rxcdrhold port must be asserted High when the RX SDI mode is SD-SDI. The LPM and DFE must be disabled for SD-SDI and enabled for other SDI line rates. The RXCDR_CFG2 attribute is modified when switching into HD-SDI, 3G-SDI, 6G-SDI, and 12G-SDI modes to optimize the CDR for the current line rate. The RXOUT_DIV attribute controls the serial clock divider for the GTH RX. The GTH RX must be reset using the gtwiz_reset_rx_datapath_in port of the GT Wizard after dynamic changes are made to any of these four conditions. If more than one of these things changes during the same SDI mode change sequence, only a single gtwiz_reset_rx_datapath_in is required after all changes have been made.

The SDI wrapper has two reset inputs for the RX section:

  • rx_rst_in: When asserted High, this input resets the SDI RX data path in the UHD-SDI core, RX controller module, and RX portion of the GTH transceiver.
  • gth_wiz_reset_rx_pll_and_datapath_in: When asserted High, this input resets both the PLL associated with the RX and then the RX section of the GTH transceiver.