The example SDI demonstration application is included with this application note. The source code for this demonstration is provided in Verilog only. Instructions for building these demonstrations using the AMD Vivado™ IDE are included in the readme.txt file located in the xapp1248-smpte-sdi-interfaces-ultrascale-gth-transceivers.zip file along with the source code. Pregenerated FPGA configuration files are also provided for the demonstration that can be loaded onto an AMD UltraScale™ FPGA KCU105 evaluation board. This demonstration require an inrevium TB-FMCH-12GSDI FMC, which provides the SDI cable drivers and SDI cable equalizers connected to the FMC connector of the KCU105 board. The inrevium FMC also provides SDI-specific clock sources that are used as reference clocks for the GTH transceivers.