For the SDI Wrapper Support and SDI Wrapper, only the periods of the FPGA IOB ports for GTH reference clocks (MGTREFCLK0/1P/N) and the GTH DRP clock need to be constrained.
The rxusrclk and txusrclk clocks no longer need to
be constrained as they are automatically constrained within the GTH Wizard IP and
are constrained depending on the maximum target line rate. For 6G-SDI and below, it
is usually 148.5 MHz; for 12G-SDI it usually 297 MHz.
The UHD-SDI wrapper contains the NI-DRU used to recover data in SD-SDI mode. The NI-DRU only runs in SD-SDI mode and in that mode, the RXOUTCLK has a frequency of 148.5 MHz. In applications that support 12G-SDI, the RXOUTCLK is constrained to 297 MHz and the NI-DRU usually does not meet timing at 297 MHz. But, it doesn't need to because it is only active when RXOUTCLK is 148.5 MHz. An additional set of constraints can be applied to the NI-DRU so that the NI-DRU is constrained to 148.5 MHz while the rest of the RX section is constrained to 297 MHz. The following two constraints are used in the example design to accomplish this:
set_property KEEP_HIERARCHY true [get_cells \ uhdsdi_demo/sdi_4ch_rxtx/genblk1[0].sdi_wrapper_support/sdi_wrapper/uhdsdi_kugth_ctrl/NIDRU]
create_generated_clock -name nidru_clk0 -source [get_pins -of [get_clocks rxoutclk_out[0]]] \
-divide_by 2 [get_pins \ uhdsdi_demo/sdi_4ch_rxtx/genblk1[0].sdi_wrapper_support/sdi_wrapper/uhdsdi_kugth_ctrl/NIDRU/ \ Inst_dru/CLK]
A KEEP_HIERARCHY constraint is applied to the NI-DRU module so that the clock name
that must be identified in the next constraint is not changed by synthesis. The
get_cells portion of this constraint uses a path to the NI-DRU
of SDI/GTH Control/NIDRU. In the example design, the UHD-SDI wrapper has an instance
name of SDI. Change the SDI portion of this path to the instance name of the UHD-SDI
wrapper in your application. The KEEP_HIERARCHY constraint is only applied for
synthesis and does not apply for implementation so it does not interfere with any
optimizations that the implementation tool may perform.
The create_generated_clock constraint creates a hierarchical clock
just for the NI-DRU. This is not a physically separate clock. It is a logical clock
used for timing analysis only. The NI-DRU is still driven by the RXOUTCLK of the
GTH. This constraint tells the timing analyzer that the clock connected to the
NI-DRU's CLK port is derived from the GTH RXOUTCLK but is half the maximum
frequency. RXOUTCLK is constrained to 297 MHz so the NI-DRU is constrained to 148.5
MHz. The AMD Vivado™ Design Suite considers all clocks to be related
unless specified. The various clocks of the SDI wrapper are generally unrelated so a
constraint is required to specify that these clocks are not related.
See the timing constraints files of the example SDI demonstration provided with this application note for examples of setting these constraints.