In SD-SDI mode, the rxusrclk of the GTH RX is technically not a
recovered clock because the CDR unit is locked to the frequency of the reference clock,
not to the SD-SDI bit stream. The only signal available that actually indicates the data
rate of the incoming SD-SDI bit stream is the 27 MHz rx_ce_out output
of the SDI Wrapper. For some video applications, particularly those that do not need to
retransmit the recovered video over an SDI interface, the rx_ce_out
port may be sufficient as a recovered clock. Typically, this signal is used as a clock
enable to downstream modules that are clocked with the rxusrclk from
the GTH RX, similar to how the SDI data path in the UHD-SDI core works by using the
rx_ce_out port as a clock enable.
If the received video data is to be retransmitted as an SD-SDI signal using a
GTH TX, a low-jitter recovered clock is required. The recovered clock must have low
enough jitter that it can be used as a reference clock for the PLL generating the serial
clock for the GTH TX. Furthermore, the frequency of the recovered clock must be 148.5
MHz so that the GTH TX can use 11x oversampling to transmit the 270 Mbps SD-SDI data.
This requires the use of an external, low-bandwidth PLL that can perform jitter
attenuation. The bandwidth of the mixed-mode clock manager (MMCM) in the UltraScale device is too high to adequately filter out the
large amounts of low frequency jitter present on the rx_ce_out port from the SDI receiver. The Texas Instruments LMH1983 and
the Silicon Labs Si5328 can both perform this function. Both of these devices can take
in the rx_ce_out port as a 27 MHz reference and
multiply it up to 148.5 MHz while also filtering out the jitter. The resulting clock is
suitable for use as a reference clock for the GTH TX. The pass-through demo included
with this application note uses a Si5328 to generate a 148.5 MHz reference clock for the
GTH TX from the 27 MHz rx_ce_out port in exactly this
manner in SD-SDI mode. When retransmitting HD-SDI, 3G-SDI, 6G-SDI, or 12G-SDI, the same
Si5328 is reprogrammed to filter jitter from the rxusrclk output of the GTH RX, doubling its frequency in the case of
HD-SDI, thereby producing a low-jitter 148.5 MHz reference clock for the GTH TX.
Another option is to use an external genlock PLL and lock it to the video sync
signals from the recovered video. The output of the genlock PLL is an SD-SDI recovered
clock. A recovered clock is sometimes required to drive external video
application-specific standard product (ASSP) devices. In SD-SDI mode, such a clock
probably must have a frequency of 27 MHz and have lower jitter than is present on the
rx_ce_out port, but does not need to have very low
jitter as is the case when producing a GTH TX reference clock. The previously-mentioned
techniques can be used, but it may be preferable to generate such a recovered clock
entirely in the FPGA without requiring external components. Unfortunately, the jitter on
the rx_ce_out port is too high to allow it to be used
directly as a reference clock input to the UltraScale MMCM. But, there is a way to generate a recovered SD-SDI clock using a spare GTH TX
as shown in the following figure.
The control module's recclk_txdata port can be
connected to the gtwiz_userdata_tx_in port of an extra
GTH TX of GTH Wizard IP. The GTH TX must use the same reference clock as the GTH RX that
is receiving the SDI input signal. The rxusrclk can be
routed to gtrefclk0_in of the GT Wizard IP and the txpllclksel_in must be set to use CPLL. The GTH TX must be configured for
a line rate of 2.97 Gbps with no encoding and with a 20-bit gtwiz_userdata_tx_in port.
When configured in this manner, the serial output of the GTH TX is a 270 MHz clock that is frequency locked to the incoming SD-SDI signal. In other words, it is a true recovered clock for SD-SDI. The GTH TX serial output pins can be connected to a global or regional clock LVDS input of the UltraScale FPGA, with appropriate care to properly terminate the CML outputs and translate them to LVDS. Then the 270 MHz clock can be used in whatever manner is required in the FPGA. For example, it can be divided by 10 to get a 27 MHz recovered clock to drive internal or external video data paths. The signal has low enough jitter that it can be used as a reference clock to an MMCM.
The recclk_txdata port of the DRU is not wired from the SDI control
module to an output port of the SDI wrapper. However, if an application must use this
feature, the SDI wrapper can be edited to add this output port.
The GTH TX that is used to generate the recovered SD-SDI clock does not have to
be configured for SDI. It only must be configured to always run a 2.97 Gbps with no
encoding. The data supplied to the gtwiz_userdata_tx_in
port of the GTH Wizard IP from the recclk_txdata port
of the control module creates a 270 MHz clock on the GTH TX serial output pins. The
edges of the generated clock move around by ± one bit time of the 2.97 Gbps line rate to
modify the frequency of the output signal so as to exactly match with the bit rate of
the input SD-SDI signal. Thus, the cycle-to-cycle jitter on the 270 MHz clock generated
by the GTH TX is ±337 ps plus whatever jitter is inherent in the GTH TX output signal (1
bit time at 2.97 Gbps is 337 ps), seen in the following figure.
In this figure, the top trace is the 270 MHz clock generated by the GTH TX. The scope was triggered on the rising edge of the recovered clock at the center of the screen. Looking at the rising edges of the cycles on either side of the trigger point, it is easy to see the ±-337 ps cycle-to-cycle jitter as these rising edges each have three discrete rising points. The bottom trace is the SD-SDI that is being retransmitted by another GTH TX.