GTH Transceiver Reference Clocks

UltraScale GTH transceivers are grouped into Quads. Each Quad contains four GTHE3_CHANNEL transceiver primitives and one GTHE3_COMMON primitive containing two Quad PLLs (QPLL0 and QPLL1) as shown in the following figure. The clock generated by the QPLL0 and QPLL1 is distributed to all four transceivers in the Quad. Each GTHE3_CHANNEL has its own PLL called the channel PLL (CPLL), which can provide a clock to the RX and TX of that transceiver only. Each RX and TX unit in the Quad can be individually configured to use either or both QPLL0 and QPLL1 or the CPLL as its clock source. Furthermore, any RX or TX unit can dynamically switch its clock source between QPLL0, QPLL1, and CPLL. This configuration and the dynamic switching capability are particularly useful for SDI applications.

Figure 1. UltraScale GTH Transceiver Quad Configuration

Typical UHD-SDI applications require the GTH transceivers to support nine different bit rates:

• 270 Mbps for SD-SDI
• 1.485 Gbps for HD-SDI
• 1.485/1.001 Gbps for HD-SDI
• 2.97 Gbps for 3G-SDI
• 2.97/1.001 Gbps for 3G-SDI
• 5.94 Gbps for 6G-SDI
• 5.94/1.001 Gbps for 6G-SDI
• 11.88 Gbps for 12G-SDI
• 11.88/1.001 Gbps for 12G-SDI

The CDR unit in the RX section of the GTH transceiver can support receiving bit rates that are up to ± 1250 ppm from the reference frequency at bit rates less than 6.6 Gbps. HD-SDI, 3G-SDI, 6G-SDI, and 12G-SDI each have two bit rates that differ by exactly 1000 ppm. For HD-SDI, 3G-SDI, and 6G-SDI, both bit rates can be received using a single reference clock frequency. That same reference clock frequency can also support reception of SD-SDI. Thus, for all SDI modes except 12G-SDI, a single RX reference clock frequency is required. However, at 12G-SDI rates, the CDR unit has only ±200 ppm tolerance relative to the reference clock frequency. Thus two different reference clock frequencies are needed to receive the two 12G-SDI bit rates. These two reference clock frequencies are typically 148.5 MHz to receive 11.88 Gbps and 148.5/1.001 MHz to receive 11.88/1.001 Gbps.

Therefore, most SDI applications provide two separate reference clocks to the GTH Quad. Usually, the supplied reference frequency pair are 148.5 MHz and 148.5/1.001 MHz. This application note always refers to the reference clock frequency pair 148.5 MHz and 148.5/1.001 MHz.

The source of the GTH transceiver reference clocks is application specific. The receiver reference clock source can be a local oscillator because it does not need to exactly match the incoming SDI bit rate. However, because the GTH transmitter line rate is always a multiple of the reference clock frequency, the frequency of the transmitter reference clock must be exactly related to the data rate of the transmitted data. Most often, the transmitter reference clocks are generated by generator locking (genlock) PLLs, thereby deriving the GTH transmitter line rate from the studio video reference signal. In some cases, such as the SDI pass-through connection, the transmitter line rate is derived from the recovered clock of the GTH receiver that is receiving the SDI signal. In such cases, an external PLL is required to reduce the jitter on the recovered clock before using it as the transmitter reference clock.

In a typical UHD-SDI application, the two reference clocks are connected to the QPLL0 and QPLL1. The RX and TX units of each transceiver in the Quad dynamically switch between the PLL clocks, depending on the bit rate that is required at the moment. The GTH txsysclksel and rxsysclksel ports are used to select the TX and RX units serial clock source between the PLLs. This common configuration for SDI applications is shown in the following figure. In this figure, multiplexers that are not used dynamically in the implementation have been replaced with wires and the reference clock routing between Quads is not shown. It is also possible to connect one reference clock to CPLL and the other to QPLL0/1 provided that only one 12G-SDI bit rate is supported.

Also, each GTH RX and TX unit has a serial clock divider that divides the selected clock by several selectable integer powers of two. This allows, for example, all of the RX units in the Quad to use the same clock frequency from the QPLL but operate at different lines rates by using different serial clock divider values. This is very useful for SDI interfaces because the 3G-SDI, 6G-SDI, and 12G-SDI bit rates are exactly twice as fast as the HD-SDI, 3G-SDI, and 6G-SDI bit rates, respectively. For 270 Mbps SD-SDI, the GTH transceiver runs at the 3G-SDI line rate using 11X oversampling techniques. The ability of the RX and TX units to locally divide the clock source by four divisors that differ by a factor of two is important, allowing reception and transmission of all SDI bit rates using two reference clock frequencies.

The serial clock divider value of each RX and TX unit can be changed dynamically through the DRP by using the RXOUT_DIV and TXOUT_DIV attributes. The configuration shown in the following figure is an optimal solution for most SDI applications for the following reasons:

• The receivers can receive all SDI bit rates when using QPLL0 and QPLL1 to provide the serial clock derived from that reference clock to all receivers in the Quad.
• The transmitters have the flexibility to dynamically switch between the clocks from QPLL0 and QPLL1 to get both frequencies they need to transmit all supported SDI bit rates.
• All four receivers and all four transmitters in the Quad are fully independent and can each run at different SDI bit rates and dynamically switch between bit rates without disrupting the other RX or TX units.
• For genlock applications, modern genlock PLLs usually can simultaneously provide both required reference clock frequencies from the synchronization reference input signal.

Figure 2. Typical GTH Reference Clock Implementation for SDI

In some SDI applications, it might be necessary for different SDI transmitters to run at slightly different bit rates although they are transmitting at the same nominal bit rate. This is often the case with SDI routers where the bit rate of each TX must exactly match the bit rate of the SDI signal received by the SDI RX to which the TX is currently connected. In these cases, two transmitters that transmit at the same nominal bit rate have bit rates that differ by a few ppm.

Supporting such applications is possible with the UltraScale GTH Quad architecture because each TX unit has exclusive use of its own CPLL. But to accomplish this, each CPLL must be provided with its own individual reference clock frequency and the number of GTH reference clock inputs is limited. There are two reference clock inputs per GTH Quad. A Quad can use reference clocks. Thus, it is possible to provide some GTH Quads in the device with five different reference clock frequencies (one for the RX and four for the four TX units), but overall, there are not enough reference clock inputs for every GTH TX in the device to have its own reference clock. The phase interpolator controlled crystal or Xtal oscillator (PICXO) technique can be very useful in these cases because it allows a GTH TX to be pulled by a few hundred ppm away from the frequency of its serial clock. Thus, applications where the bit rate of each SDI TX must be individually locked to the bit rate of the received SDI signal can be implemented by using common reference clocks as shown in the previous figure, then using the PICXO technique with each GTH TX to set the exact bit rate of each SDI transmitter individually. This application note does not cover the PICXO technique. For further information about using PICXO, contact Technical Support at the Support web page.