The following table lists the parameters that can be applied to the SDI wrapper.
| Name | Type | Default | Description |
|---|---|---|---|
| UHD-SDI GTH TX Controller Parameters | |||
| TXPLLCLKSEL_TX_M_0 | Binary | 2'b11 | This parameter specifies the value driven to the
txpllclksel pin of GTHE3_CHANNEL when tx_m_in is Low. Valid values are 2'b00 (CPLL), 2'b11 (QPLL0) and 2'b10 (QPLL1). |
| TXPLLCLKSEL_TX_M_1 | Binary | 2'b10 | This parameter specifies the value driven to the
txpllclksel pin of GTHE3_CHANNEL when tx_m_in is High. Valid values are 2'b00 (CPLL), 2'b11 (QPLL0) and 2'b10 (QPLL1). |
| UHD-SDI GTH RX Controller Parameters | |||
| EN_HOT_PLUG_LOGIC | Binary | 1'b0 | This parameter enables the Hot Plug when rx_mode_detect_in is Low. |
| RX_FXDCLK_FREQ | Integer | 27000000 | This parameter specifies the frequency, in Hz, of the fixed-frequency clock on the clk port of the SDI wrapper. The nominal frequency of this clock must be correctly specified so that the portions of the control module that depend on this clock for timing function correctly. |
| RXPLLCLKSEL_TX_M_0 | Binary | 2'b11 | This parameter specifies the value driven to the
rxpllclksel pin of GTHE3_CHANNEL for all rx_mode_out value except
3'b110. Valid values are 2'b00 (CPLL), 2'b11 (QPLL0) and 2'b10 (QPLL1). |
| RXPLLCLKSEL_TX_M_1 | Binary | 2'b10 | This parameter specifies the value driven to the
rxpllclksel pin of GTHE3_CHANNEL when rx_m_out is High and
rx_mode_out is 3'b110. Valid values are 2'b00 (CPLL), 2'b11 (QPLL0) and 2'b10 (QPLL1). |
| GTH Wizard IP Parameters | |||
| XY_SITE | String | "x0y16" | This parameter specifies the GTH Wizard IP instance location in the FPGA. |