FPGA Resource Usage

The following table shows the FPGA resources required for an SDI interface with a Kintex UltraScale GTH transceiver. The resource usage includes all the modules required to implement the interface included in one SDI Wrapper Support instance. Resource usage is shown for various common configurations.

The results shown were achieved with Vivado Design Suite 2023.1.

The SDI receiver and transmitter interface designs do not use any MMCM clock managers. And, they do not require any block RAMs or DSP blocks.

Typically, one global or regional clock is required for each SDI TX and for each SDI RX. In addition, one fixed frequency global clock is required for timing in the SDI wrapper. This fixed frequency clock is usually also used as the GTH DRP clock. Only one such fixed frequency global clock is required regardless of the number of SDI interfaces are implemented in the FPGA.

Constraints

Example constraint files are provided with the reference designs and can be used as examples of the timing and placement constraints required for SDI interfaces. Typically, the only timing requirements are period constraints on the GTH transceiver reference clock IOB pins and the fixed frequency clock used for the DRPCLK and the SDI Wrapper's rx_fxdclk_in port. The GTH reference clocks constraints should specify the period of these clocks as 148.5 MHz (often rounded up to 150 MHz). I/O placements and clock constrains for the GTH transceivers are already specified within each GTH Wizard IP.