In this use model, shown in Figure 1, there are multiple transceivers active in the quad. All of the receivers are clocked by QPLL1. Each transmitter is clocked only by QPLL0. This multi-link use model is the recommended clocking for SDI TX and SDI RX if either 12G-SDI integer bit rate or 12G-SDI fractional bit rate support but not both is required. The CPLL is required to implement different protocols other than SDI in other transceivers of the same quad if less than four transceivers are used.
The following connections must be made:
- Connect the reference clocks to the
gth_qpll0_refclk_p
/n_in
andgth_qpll1_refclk_p
/n_in
ports. - The
gth_cpll_refclk_p_in
andgth_cpll_refclk_n_in
ports must be connected to zero. - The
gth_drpclk_in
must be connected to the clock specified during GTH Wizard IP generation. In this application note it is 27 MHz. - The
gth_wiz_reset_tx_pll_and_datapath_in
input port must be Low only when the reference clock source to the QPLL0 is stable. - The
gth_wiz_reset_rx_pll_and_datapath_in
input port must be Low only when the reference clock source to the QPLL1 is stable. - The RXPLLCLKSEL_RX_M_0 parameter of the SDI Wrapper Support and SDI Wrapper must be set to 2'b10 (QPLL1).
- The RXPLLCLKSEL_RX_M_1 parameter of the SDI Wrapper Support and SDI Wrapper must be set to 2'b10 (QPLL1).
- The TXPLLCLKSEL_TX_M_0 parameter of the SDI Wrapper Support and SDI Wrapper must be set to 2'b11 (QPLL0).
- The TXPLLCLKSEL_TX_M_1 parameter of the SDI Wrapper Support and SDI Wrapper must be set to 2'b11 (QPLL0).
- When the QPLL0 must be reset due to a reference clock change or interruption, assert
the
gth_qpll0_reset_in
input of the SDI Wrapper Support. - When the QPLL1 must be reset due to a reference clock change or interruption, assert
the
gth_qpll1_reset_in
input of the SDI Wrapper Support. - The SDI Wrapper Support
qpll0
/1_clk
,qpll0
/1_refclk
andqpll0
/1_lock
output ports must be connected to their corresponding ports in the SDI Wrapper.