Receiving SD-SDI

The 270 Mbps bit rate of SD-SDI is below the minimum line rate supported by the GTH RX. To receive 270 Mbps SD-SDI, the GTH RX is used as an asynchronous oversampler to sample the SD-SDI bit stream at 11 times 270 Mbps (2.97 G samples/sec) without regard to where bit transitions occur. The CDR unit in the GTH RX is locked to the reference clock by asserting the GTH transceiver's rxcdrhold input port High. This prevents the CDR from trying to lock to the slow SD-SDI signal and results in more uniform oversampling of the SD-SDI signal.

When receiving an SD-SDI signal, the auto adaptation feature of the low power mode (LPM) and Decision feedback equalization (DFE) equalizer must be disabled. The long run lengths at the slow bit rate cause problems for the equalizers. The LPM auto adaptation feature is disabled by asserting the following ports of the GTHE3_CHANNEL primitive High:

RXLPMGCOVRDEN
RXLPMHFOVRDEN
RXLPMLFKLOVRDEN
RXLPMOSOVRDEN
RXOSOVRDEN

The DFE equalization is disabled by asserting the following ports of the GTHE3_CHANNEL primitive High:

RXDFEAGCOVRDEN
RXDFELFOVRDEN
RXDFETAP2OVRDEN
RXDFETAP3OVRDEN
RXDFETAP4OVRDEN
RXDFETAP5OVRDEN
RXDFETAP6OVRDEN
RXDFETAP7OVRDEN
RXDFETAP8OVRDEN
RXDFETAP9OVRDEN
RXDFETAP10OVRDEN
RXDFETAP11OVRDEN
RXDFETAP12OVRDEN
RXDFETAP13OVRDEN
RXDFETAP14OVRDEN
RXDFETAP15OVRDEN
RXDFEUTOVRDEN

With the UltraScale FPGAs Transceiver Wizard, these ports are not enabled by default on the GTH Wizard IP and need to be manually enabled. These ports can be found in the Structural Options tab of the wizard with _in suffixes as port names. The easiest thing to do is to connect the rxcdrhold_in port of the GTH wrapper to these ports of the GTH Wizard IP. The rxcdrhold_in port is driven High by the SDI control logic when the receiver is in SD-SDI mode, so these three ports are driven High in SD-SDI mode if connected in this manner.

A data recovery unit (DRU), implemented in the programmable logic of the FPGA, examines the oversampled SD-SDI data from the GTH RX, determines the most likely value for each bit, and outputs the recovered data. This DRU is not part of the UHD-SDI core, but is provided as part of this applications note's SDI control module.

The DRU provided with this application note is described in Clock and Data Recovery Unit based on Deserialized Oversampled Data (XAPP1240). That application note does describe the theory of operation of the DRU, but is not necessary for use of the DRU in the UHD-SDI reference design.

SMPTE ST 259 (the SD-SDI standard) specifies several other bit rates besides 270 Mbps. The DRU is instantiated into the SDI control module so as to support only 11x oversampling of 270 Mbps serial data. However, if other SD-SDI bit rates need to be supported by the application, the DRU can be used to receive those bit rates as well. Because that DRU supports fractional oversampling factors, it is possible to receive the other SD-SDI bit rates without requiring any additional RX reference clock frequencies. Note that the 540 Mbps SD-SDI bit rate specified by SMPTE ST 344 is within the supported line rate range of the GTH transceiver and thus the GTH RX does not need to use the DRU to receive it. However, receiving the 540 Mbps bit rate without the DRU requires a different reference clock frequency than is used for the other SDI bit rates. Thus, it is usually more convenient to use the DRU to receive the 540 Mbps ST 344 signal using 5.5X oversampling so that the standard SDI reference clock frequency can be used. AMD does not have an example design supporting additional SD-SDI bit rates.

The DRU does not recover a clock and, because the CDR unit in the GTH RX is locked to its reference clock, the rxusrclk is not locked to the incoming bit rate in SD-SDI mode. The DRU produces a data strobe in rxusrclk clock domain indicating when a 10-bit data word is ready on its output. This data strobe is used by the UHD-SDI core to generate a clock enable that is asserted at a 27 MHz rate, typically with a 5|6|5|6 cadence relative to the rxusrclk clock from the GTH. The rx_ce_out output of the v_smpte_uhdsdi_rxtx wrapper during SD-SDI operations is derived from the DRU data strobe and has the same cadence. Occasionally the cadence of the DRU data strobe and the rx_ce_sd signal varies from the typical 5|6|5|6 cadence. This occurs when the DRU must make up for the slight difference between the actual SD-SDI bit rate and the frequency of the local reference clock provided to the PLL used by the GTH RX.

The following figure shows a screen capture from an oscilloscope showing the 27 MHz rx_ce_out port during SD-SDI operation.

Figure 1. Oscilloscope Capture of SD-SDI Clock Enable

The scope is triggered on the rising edge of rx_ce_out at the center of the screen. The scope is in infinite persistence mode and the waveform was allowed to accumulate for several minutes. The waveform is temperature-coded from red (indicating the most common position of the signal), to blue (indicating the least common position). The incoming SD-SDI signal that was used to create this screen capture was asynchronous to the local reference clock used by the GTH receiver. The rx_ce_out pulses on either side of the center pulse are always 5 or 6 clock cycles away from the center pulse because of the 5|6|5|6 cadence of the rx_ce_out port. The two pulses at the far right and far left of the trace are nominally 11 clock cycles from the center pulse because of the 5|6|5|6 cadence. The nominal position is marked by the yellow and red pulse. For the far right pulse, the dashed yellow vertical cursor marks the position that is 11 clock cycles from the rising edge of the center pulse. The nominal location of the central yellow/red pulses are surrounded on either side by blue pulses indicating that, occasionally, the DRU must make the period of the rx_ce_out cycle either 10 clock cycles or 12 clock cycles long to compensate for the frequency differences between the local reference clock and the incoming SD-SDI signal. Refer to the SMPTE UHD-SDI LogiCORE IP Product Guide (PG205) for more information.

The SD-SDI DRU is supplied with this application note as an encrypted, pre-generated file called nidru_20_wrapper.vhd. The encryption used on the DRU is compatible with most synthesis and simulation software.