GTH TX Resets

The UltraScale FPGAs Transceiver Wizard offers three ways to reset the TX portion of the GTH Transceiver:

• gtwiz_reset_all_in: Asserted High. User signal to reset both TX and RX portions phase-locked loops (PLLs) and active data directions of GTH transceiver. This reset is affected for TX and RX GTH portions and is thus normally asserted during startup condition.
• gtwiz_reset_tx_pll_and_datapath_in: Asserted High. User signal to reset the TX data direction and associated PLLs of the GTH transceiver. This reset is particularly useful if the reference clock to the TX PLL changes.
• gtwiz_reset_tx_datapath_in: Asserted High. User signal to reset the TX data direction of transceiver primitives. This reset is asserted for SDI TX application when at least one of the tx_mode, tx_m, and tx_mux_pattern ports change.

For use cases that use one of the QPLLs and one CPLL, the two PLL types have different operating frequency ranges. For SDI applications, the serial clocks from the QPLLs are twice the frequency of the serial clock from the CPLL. Thus, when the tx_m input port of the SDI wrapper changes to request a dynamic switch of the GTH TX between the two PLLs, a dynamic change of the serial clock divider through the TXOUT_DIV DRP attribute must also be done at the same time if the transmitter remains in the same SDI mode. For example, when switching from an HD-SDI bit rate of 1.485 Gbps using the QPLL as the serial clock source to an HD-SDI bit rate of 1.485/1.001 Gbps using the CPLL as the serial clock source, both the txsysclksel port and TXOUT_DIV DRP attribute must be changed. However, if the SDI mode, as selected by the tx_mode input port of the SDI wrapper, changes at the same time as the tx_m port, the serial clock divider may or may need to be changed. For example, if changing from HD-SDI mode using the CPLL to the 3G-SDI mode using the QPLL, the txrate port does not need to change because changing from the CPLL to the QPLL inherently increases the serial clock frequency and the resulting line rate by a factor of two.

The tx_mode port dictates the data width of the GTH transceiver. For example, at 6G-SDI or 12G-SDI, the GTH internal and user interface data width have to be changed to 4 bytes and 40 bits, respectively. The same parameters are set to 2 bytes and 20 bits for the lower bit rates. The data widths of the UHD-SDI TX and TX portion of the GTH transceiver should always match. This is done in the GTH transceiver by modifying the RX_DATA_WIDTH and RX_INT_DATAWIDTH DRP attributes which affects the interface and internal data width, respectively.

Because tx_mode and tx_m are separate input ports to the SDI wrapper, when one of these ports changes, a small settling delay is implemented before the txsysclksel port, TXOUT_DIV, RX_DATA_WIDTH, and RX_INT_DATAWIDTH DRP attributes are dynamically changed. This setting delay allows a short window of time for the other port to also change before the TX control logic decides whether these port and DRP attributes need to change. The SDI wrapper has two reset inputs for the TX section:

• tx_rst_in: When asserted High, this input resets the SDI TX data path in the UHD-SDI core, TX controller module, and TX portion of the GTH transceiver.
• gth_wiz_reset_tx_pll_and_datapath_in: When asserted High, this input resets both the PLL associated with the TX and then the TX section of the GTH transceiver.