Use Model 1: A Single Transceiver Active in the Quad, RX and TX are Dynamically Clocked by QPLL0 and QPLL1

In this use model, shown in the following figure, there is a single transceiver active in the quad with the RX and TX serial clocks provided by either QPLL0 or QPLL1. This use model is the recommended clocking if both 12G-SDI bit rates are supported. This use model is the recommended clocking for both SDI TX and SDI RX if either 12G-SDI integer bit rate or 12G-SDI fractional bit rate support but not both is required. The CPLL is required to implement different protocols other than SDI in other transceivers of the same quad.

The following connections and configurations must be made:

• Connect the reference clocks 148.5 MHz and 148.35 MHz to the gth_qpll0_refclk_p/n_in and gth_qpll1_refclk_p/n_in ports respectively.
• The gth_cpll_refclk_p_in and gth_cpll_refclk_n_in ports must be connected to zero.
• The gth_drpclk_in must be connected to the clock specified during GTH Wizard IP generation. In this application note it is 27 MHz.
• The gth_wiz_reset_tx_pll_and_datapath_in and gth_wiz_reset_rx_pll_and_datapath_in input ports must be Low only when the reference clock source to the QPLL0 and QPLL1 is stable.
• The RXPLLCLKSEL_RX_M_0 parameter of the SDI Wrapper Support must be set to 2'b11 (QPLL0).
• The RXPLLCLKSEL_RX_M_1 parameter of the SDI Wrapper Support must be set to 2'b10 (QPLL1).
• The TXPLLCLKSEL_TX_M_0 parameter of the SDI Wrapper Support must be set to 2'b11 (QPLL0).
• The TXPLLCLKSEL_TX_M_1 parameter of the SDI Wrapper Support must be set to 2'b10 (QPLL1).
• When the QPLL0 must be reset due to a reference clock change or interruption, assert the gth_qpll0_reset_in input of the SDI Wrapper Support.
• When the QPLL1 must be reset due to a reference clock change or interruption, assert the gth_qpll1_reset_in input of the SDI Wrapper Support.