GTH PLL Use Models for SDI Applications

This section describes several typical configurations of PLLs and transceivers used in SDI applications. Not every possible configuration is described, but the configurations shown here sufficiently describe the proper connection of the PLL reset and locked signals.

The SDI wrapper has four static parameters that specify which serial clock sources come from the QPLLs and which come from the CPLL. These attributes do not control the routing of PLL clocks and are only used to calculate the correct RX and TX serial clock divider values and, for the TX, the value to drive onto the GTH Wizard IP rxpllclksel_in and txpllclksel_in ports based on the current value of rx_m and tx_m respectively. These four parameters are two-bit binary values and must be assigned values as described here:

• The RXPLLCLKSEL_RX_M_0 parameter must be set to 2'b00 (CPLL) or 2'b11 (QPLL0) or 2'b10 (QPLL1) depending on the clock source for the GTH RX when rx_m is Low.
• The RXPLLCLKSEL_RX_M_1 parameter must be set to 2'b00 (CPLL) or 2'b11 (QPLL0) or 2'b10 (QPLL1) depending on the clock source for the GTH RX when rx_m is High and rx_mode is 3'b110 (12G 11.88/1.001 Gbps).
• The TXPLLCLKSEL_TX_M_0 parameter must be set to 2'b00 (CPLL) or 2'b11 (QPLL0) or 2'b10 (QPLL1) depending on the clock source for the GTH TX when tx_m is Low.
• The TXPLLCLKSEL_TX_M_1 parameter must be set to 2'b00 (CPLL) or 2'b11 (QPLL0) or 2'b10 (QPLL1) depending on the clock source for the GTH TX when tx_m is High.

There are two parameters for the RX clock to support dynamic switching of the RX between the two PLL clock sources using the rx_m port of the SDI wrapper. RXPLLCLKSEL_RX_M_0 is used to drive the rxpllclksel_in of GT Wizard IP when tx_m is Low, and RXPLLCLKSEL_RX_M_1 is used when rx_m is High and rx_mode is 3'b110 (12G-SDI /1.001). In applications where the RX PLL is not dynamically switched, set the same value for both RXPLLCLKSEL_RX_M_0 and RXPLLCLKSEL_RX_M_1 depending on the clock source to the RX PLL.

Similar to RX, there are two parameters for the TX clock to support dynamic switching of the TX between the two PLL clock sources using the tx_m port of the SDI wrapper. TXPLLCLKSEL_TX_M_0 is used to drive the txpllclksel_in when tx_m is Low and TXPLLCLKSEL_TX_M_1 is used when tx_m is High. In applications where the TX PLL is not dynamically switched, set the same value for both TXPLLCLKSEL_TX_M_0 and TXPLLCLKSEL_TX_M_1 depending on clock source to TX PLL.