Use Model 5: A Single Transceiver Active in the Quad, RX Is Clocked by QPLL1 and TX Is Dynamically Clocked by QPLL1 and CPLL

In this use model, shown in the following figure, there is a single transceiver active in the quad with the RX serial clock provided by QPLL1 and TX serial clock provided by either QPLL1 or CPLL. This use model is the recommended clocking for both SDI TX and SDI RX if either 12G-SDI integer bit rate or 12G-SDI fractional bit rate support but not both is required. QPLL0 is required to implement different protocols other than SDI in other transceivers of the same quad. The following connections must be made:

• Connect one reference clock to the gth_qpll1_refclk_p_in and gth_qpll1_refclk_n_in ports.
• Connect one reference clock to the gth_cpll_refclk_p_in and gth_cpll_refclk_n_in ports.
• The gth_qpll0_refclk_p_in and gth_qpll0_refclk_n_in ports must be connected to zero.
• The gth_drpclk_in must be connected to the clock specified during GTH Wizard IP generation. In this application note it is 27 MHz.
• The gth_wiz_reset_tx_pll_and_datapath_in input port must be Low only when the reference clock source to the QPLL1 and CPLL is stable.
• The gth_wiz_reset_rx_pll_and_datapath_in input port must be Low only when the reference clock source to the QPLL1 is stable.
• The RXPLLCLKSEL_RX_M_0 parameter of the SDI Wrapper Support must be set to 2'b10 (QPLL1).
• The RXPLLCLKSEL_RX_M_1 parameter of the SDI Wrapper Support must be set to 2'b10 (QPLL1).
• The TXPLLCLKSEL_TX_M_0 parameter of the SDI Wrapper Support must be set to either 2'b10 (QPLL1) or 2'b00 (CPLL).
• The TXPLLCLKSEL_TX_M_1 parameter of the SDI Wrapper Support must be set to either 2'b00 (CPLL) or 2'b10 (QPLL1) depending on the reference clock connection and which is not used on TXPLLCLKSEL_TX_M_0.
• When the QPLL1 must be reset due to a reference clock change or interruption, assert the gth_qpll1_reset_in input of the SDI Wrapper Support.