The following table describes all of the ports of the SDI Wrapper. This port list is similar to the port list of the UHD-SDI core itself, but there are some differences. Also refer to the example SDI applications provided with this application note for examples of how to interconnect the GTH and SDI wrappers.
Some signals are described as being asserted for some number of video sample
periods. A video sample period lasts for differing numbers of cycles of the
appropriate clock (either txusrclk or rxusrclk) depending on the SDI mode. In HD-SDI and
3G-SDI level A modes, a sample period lasts one clock cycle. In SD-SDI mode, a
sample period is either five or six clock cycles long and begins and ends with the
rising edge of the clock when the clock enable (either tx_sd_ce_in or rx_ce_out) is asserted.
In 3G-SDI level B mode, a sample period is two clock cycles long as controlled by
the assertion of the rx_ce_out port.
Most of the RX and TX ports in this list are wired directly to the ports of the same name plus suffix of _in or _out on the UHD-SDI core that is instantiated inside the SDI wrapper. Timing diagrams of the video and video timing signals can be found in the SMPTE UHD-SDI LogiCORE IP Product Guide (PG205).
| Port Name | I/O | Width | Description |
|---|---|---|---|
| Receive Ports | |||
| rx_fxdclk_in | In | 1 | Fixed-frequency clock SDI RX bit rate detection |
| rx_rst_in | In | 1 | Synchronous reset input. This reset is synchronous to the gth_drpclk_in port. |
| rx_usrclk_out | out | 1 | GTH rxusrclk clock output. This port is also the signal fed into the rx_clk port of the UHD-SDI core. |
| rx_mode_detect_rst_in | In | 1 | Synchronous reset that resets only the SDI mode detect search function. The SDI mode detect search function is only reset when rx_mode_detect_rst_in is High when rx_ce_out is High on a rising edge of rx_usrclk_out. |
| rx_mode_en_in | In | 6 | This port has unary bits to enable reception of each of the five SDI modes: |
| Bit 0 enables HD-SDI mode | |||
| Bit 1 enables SD-SDI mode | |||
| Bit 2 enables 3G-SDI mode | |||
| Bit 3 enables 6G-SDI mode | |||
| Bit 4 enables 12G-SDI 11.88 Gbps mode | |||
| Bit 5 enables 12G-SDI 11.88/1.001 Gbps mode | |||
|
When a bit is High, the corresponding SDI mode is enabled. When a bit is low, the receiver does not attempt to detect incoming SDI signals of that mode. Disabling unused SDI modes using these bits decreases the amount of time it takes for the receiver to lock to the incoming signal when it changes modes. |
|||
| rx_mode_detect_en_in | In | 1 |
This port enables the SDI mode detection feature when High. When enabled, the SDI mode detector controls the receiver to search for and lock to the incoming SDI data stream. When disabled, the user application must tell the SDI receiver what SDI mode to operate in using the rx_forced_mode_in port. |
| rx_forced_mode_in | In | 3 | When the rx_mode_detect_en_in input is Low, disabling the automatic SDI mode detection feature, the receiver operates in the SDI mode specified by the value on the rx_forced_mode_in port. |
| 000 = HD | |||
| 001 = SD | |||
| 010 = 3G | |||
| 100 = 6G | |||
| 101 = 12G 11.88 Gbps | |||
| 110 = 12G 11.88/1.001 Gbps | |||
| rx_mode_out | Out | 3 | This output port indicates the current SDI mode of the receiver: |
| 000 = HD | |||
| 001 = SD | |||
| 010 = 3G | |||
| 100 = 6G | |||
| 101 = 12G 11.88 Gbps | |||
| 110 = 12G 11.88/1.001 Gbps | |||
| When the receiver is not locked, the rx_mode port changes values as the receiver searches for the correct SDI mode. During this time, the rx_mode_locked output is Low. When the receiver detects the correct SDI mode, the rx_mode_locked output goes High. | |||
| rx_mode_hd_out | Out | 1 | High when RX is locked in HD-SDI mode |
| rx_mode_sd_out | Out | 1 | High when RX is locked in SD-SDI mode |
| rx_mode_3g_out | Out | 1 | High when RX is locked in 3G-SDI mode |
| rx_mode_6g_out | Out | 1 | High when RX is locked in 6G-SDI mode |
| rx_mode_12g_out | Out | 1 | High when RX is locked in 12G-SDI mode (either bit rate) |
| rx_mode_locked_out | Out | 1 | When this output is Low, the receiver is actively searching for the SDI mode that matches the input data stream. During this time, the rx_mode_out port changes frequently. When the receiver locks to the correct SDI mode, the rx_mode_locked_out output goes High. |
| When the SDI mode detect function is disabled (rx_mode_detect_en_in = Low), this output is always asserted High. In this case, it is not a reliable indicator of whether or not the SDI receiver is locked to the incoming SDI signal. | |||
| rx_bit_rate_out | Out | 1 | This is the bit rate output of the v_smpte_uhdsdi_rate_detect.v module. This port is the signal that goes into the rx_bit_rate port of the UHD-SDI core. |
|
HD-SDI mode:
rx_m_out = 0: Bit rate = 1.485 Gbps rx_m_out = 1: Bit rate = 1.485/1.001 Gbps |
|||
|
3G-SDI mode:
rx_m_out = 0: Bit rate = 2.97 Gbps rx_m_out = 1: Bit rate = 2.97/1.001 Gbps |
|||
|
6G-SDI mode:
rx_m_out = 0: Bit rate = 5.94 Gbps rx_m_out = 1: Bit rate = 5.94/1.001 Gbps |
|||
|
12G-SDI mode:
rx_m_out = 0: Bit rate = 11.88 Gbps rx_m_out = 1: Bit rate = 11.88/1.001 Gbps |
|||
| rx_t_locked_out | Out | 1 | This output is High when the transport detection function in the receiver has identified the transport format of the SDI signal. |
| rx_t_family_out | Out | 4 | This output indicates which family of video signals is being used as the transport of the SDI interface. This output is only valid when rx_t_locked is High. This port does not necessarily identify the video format of the picture being transported. It only identifies the transport characteristics. See Table 1 for the encoding of this port. |
| rx_t_rate_out | Out | 4 | This output indicates the frame rate of the transport. This is not necessarily the same as the frame rate of the actual picture. This output is only valid when rx_t_locked is High. See Table 1 for the encoding of this port. |
| rx_t_scan_out | Out | 1 | This output indicates whether the transport is interlaced (Low) or progressive (High). This is not necessarily the same as the scan mode of the actual picture. This output is only valid when rx_t_locked is High. |
| rx_level_b_3g_out | Out | 1 | In 3G-SDI mode, this output is asserted High when the input signal is level B and Low when it is level A. This output is only valid when rx_mode_3g is High. |
| rx_ce_out | Out | NUM_ RX_CE | This is the RX clock enable output. There are NUM_RX_CE copies of this clock enables on this port. These clock enables are valid in all SDI modes. In SD mode, the CEs have a nominal 5|6|5|6 cadence. In HD and 3GA modes, the CEs are always High. In 3GB mode, the CEs have a 50% duty cycle. In 6G, the duty cycle can be 100% or 50% depending on how may data streams are interleaved onto the signal. In 12G, the duty cycle can be 50% or 25% depending on how many data streams are interleaved onto the signal. This port replaces the rx_ce_sd and rx_dout_rdy_3g ports of the old core and combines their functionality by being correct for all SDI modes. |
| rx_active_streams_out | Out | 3 | This port indicates the number of data streams
that are active for the current video format being received. The
number of active data streams is 2^active_streams. 000: 1 active stream 001: 2 active streams 010: 4 active streams 011: 8 active streams 100: 16 active streams |
| rx_line_0_out | Out | 11 | Captured line number from data stream 1 is output here. Not valid in SD-SDI mode. |
| rx_line_1_out | Out | 11 | Captured line number from data stream 3 is output here. Only valid if 4 or more data streams are active. |
| rx_line_2_out | Out | 11 | Captured line number from data stream 5 is output here. Only valid if 8 or more data streams are active. |
| rx_line_3_out | Out | 11 | Captured line number from data stream 7 is output here. Only valid if 8 or more data streams are active. |
| rx_line_4_out | Out | 11 | Captured line number from data stream 9 is output here. Only valid if 16 data streams are active. |
| rx_line_5_out | Out | 11 | Captured line number from data stream 11 is output here. Only valid if 16 data streams are active. |
| rx_line_6_out | Out | 11 | Captured line number from data stream 13 is output here. Only valid if 16 data streams are active. |
| rx_line_7_out | Out | 11 | Captured line number from data stream 15 is output here. Only valid if 16 data streams are active. |
| rx_st352_0_out | Out | 32 | The ST 352 payload ID packet data bytes captured from ds1 are output here. |
| rx_st352_0_valid_out | Out | 1 | High when rx_st352_0 is valid. |
| rx_st352_1_out | Out | 32 |
The ST 352 payload ID packet data bytes captured from ds3 are output here. In 3G-SDI level A mode, the ST 352 payload ID packet data bytes from ds2 are output here. |
| rx_st352_1_valid_out | Out | 1 | High when rx_st352_1 is valid. |
| rx_st352_2_out | Out | 32 | The ST 352 payload ID packet data bytes captured from ds5 are output here. |
| rx_st352_2_valid_out | Out | 1 | High when rx_st352_2 is valid. |
| rx_st352_3_out | Out | 32 | The ST 352 payload ID packet data bytes captured from ds7 are output here. |
| rx_st352_3_valid_out | Out | 1 | High when rx_st352_3 is valid. |
| rx_st352_4_out | Out | 32 | The ST 352 payload ID packet data bytes captured from ds9 are output here. |
| rx_st352_4_valid_out | Out | 1 | High when rx_st352_4 is valid. |
| rx_st352_5_out | Out | 32 | The ST 352 payload ID packet data bytes captured from ds11 are output here. |
| rx_st352_5_valid_out | Out | 1 | High when rx_st352_5 is valid. |
| rx_st352_6_out | Out | 32 | The ST 352 payload ID packet data bytes captured from ds13 are output here. |
| rx_st352_6_valid_out | Out | 1 | High when rx_st352_6 is valid. |
| rx_st352_7_out | Out | 32 | The ST 352 payload ID packet data bytes captured from ds15 are output here. |
| rx_st352_7_valid_out | Out | 1 | High when rx_st352_7 is valid. |
| rx_crc_err_out | Out | 16 | These 16 bits are the CRC error indicator for each data stream output. Bit 0 is the CRC error indicator for data stream 1, bit 1 for data stream 2, etc. When a CRC is detected on a line, the CRC error bit corresponding to that data stream becomes asserted starting a few clock cycles after the last CRC word is output on the data stream ports following the EAV that ends the line containing the error. The CRC error bit remains asserted for one line time. These bits are not valid in SD-SDI mode. |
| rx_ds1_out | Out | 10 | Data stream 1 output. In SD mode this is interleaved Y/C. In HD and 3GA modes, this is the Y channel. In 3GB mode, this is the link A Y channel. In 6G and 12G modes, this is ds1. Same as the rx_ds1a output port of previous core. |
| rx_ds2_out | Out | 10 | Data stream 2 output. Not used in SD mode. In HD and 3GA modes, this is the C channel. In 3GB mode, this is the link A C channel. In 6G and 12G modes, this is ds2. Same as the rx_ds2a port of previous core. |
| rx_ds3_out | Out | 10 | Data stream 3 output. Not used in SD, HD, and 3GA modes. In 3GB mode, this is the link B Y channel. In 6G and 12G modes this is ds3. Same as the rx_ds1b port of previous core. |
| rx_ds4_out | Out | 10 | Data stream 4 output. Not used in SD, HD, and 3G level A modes. In 3G level B mode, this is the link B C channel. In 6G and 12G modes this is ds4. |
| rx_ds5_out | Out | 10 | Data stream 5 output. Only used in 6G and 12G modes. |
| rx_ds6_out | Out | 10 | Data stream 6 output. Only used in 6G and 12G modes. |
| rx_ds7_out | Out | 10 | Data stream 7 output. Only used in 6G and 12G modes. |
| rx_ds8_out | Out | 10 | Data stream 8 output. Only used in 6G and 12G modes. |
| rx_ds9_out | Out | 10 | Data stream 9 output. Only used in 12G mode when 16 data streams are active. |
| rx_ds10_out | Out | 10 | Data stream 10 output. Only used in 12G mode when 16 data streams are active. |
| rx_ds11_out | Out | 10 | Data stream 11 output. Only used in 12G mode when 16 data streams are active. |
| rx_ds12_out | Out | 10 | Data stream 12 output. Only used in 12G mode when 16 data streams are active. |
| rx_ds13_out | Out | 10 | Data stream 13 output. Only used in 12G mode when 16 data streams are active. |
| rx_ds14_out | Out | 10 | Data stream 14 output. Only used in 12G mode when 16 data streams are active. |
| rx_ds15_out | Out | 10 | Data stream 15 output. Only used in 12G mode when 16 data streams are active. |
| rx_ds16_out | Out | 10 | Data stream 16 output. Only used in 12G mode when 16 data streams are active. |
| rx_eav_out | Out | 1 | This output is asserted High when the XYZ word of an EAV is present on the data stream output ports. |
| rx_sav_out | Out | 1 | This output is asserted High when the XYZ word of a SAV is present on the data stream output ports. |
| rx_trs_out | Out | 1 |
This output is asserted High while the four consecutive words of any EAV or SAV are present on the data stream output ports, starting |
| rx_edh_errcnt_en_in | In | 16 | This input controls which EDH error condition increments the rx_edh_errcnt counter. See Table 2 for more details. 1 |
| rx_edh_clr_errcnt_in | In | 1 | When High, this input clears the rx_edh_errcnt counter. This input port must be High during the same clock cycle when rx_ce_sd is also High to clear the error counter. 1 |
| rx_edh_ap_out | Out | 1 | This output is asserted High when the active picture CRC calculated for the previous field does not match the AP CRC value in the EDH packet. 1 |
| rx_edh_ff_out | Out | 1 | This output is asserted High when the full field CRC calculated for the previous field does not match the FF CRC value in the EDH packet. 1 |
| rx_edh_anc_out | Out | 1 | This output is asserted High when an ancillary data packet checksum error is detected. 1 |
| rx_edh_ap_flags_out | Out | 5 | The active picture error flag bits from the most recently received EDH packet are output on this port. See Table 1 for encoding of this port. See Table 1 for more details. |
| rx_edh_ff_flags_out | Out | 5 | The full frame error flag bits from the most recently received EDH packet are output on this port. See Table 1 for encoding of this port. See Table 1 for more details. 1 |
| rx_edh_anc_flags_out | Out | 5 | The ancillary error flag bits from the most recently received EDH packet are output on this port. See Table 1 for encoding of this port. See Table 1 for more details. 1 |
| rx_edh_packet_flags_out | Out | 4 | This port outputs four error flags related to the most recently received EDH packet. See Table 2 for encoding of this port. See Table 2 for more details. 1 |
| rx_edh_errcnt_out | Out | 16 | This is the SD-SDI EDH error counter. It increments once per field when any of the error conditions enabled by the rx_edh_err_en port occur during that field. 1 |
| rx_change_done_out | Out | 1 | This output is Low during those periods when the
GTH RX is being initialized, reset, or when it is being dynamically
switched between SDI modes. If the initialization, reset, or dynamic
change sequence completes successfully, the rx_change_done_out
output is asserted High to indicate successful completion. This output is synchronous with the gth_drpclk_in. |
| rx_change_fail_out | Out | 1 | Under normal conditions, this output is always
Low. It only goes High if the control module is unsuccessful in
completing a GTH RX initialization, reset, or SDI mode change
sequence. If such a failure occurs, the rx_change_fail_out port is
asserted High and the rx_change_fail_code_out port indicates the
nature of the failure. If a failure occurs, the GTH RX must be reset
using the rx_rst_in and gth_wiz_reset_rx_pll_and_datapath_in. This output is synchronous with the gth_drpclk. |
| rx_change_fail_code_out | Out | 3 | When the rx_change_fail port is High, this port indicates the nature of the sequence failure. See Table 3 for encoding of this port. This output is synchronous with the gth_drpclk_in. |
| Transmit Ports | |||
| tx_rst_in | In | 1 | This is a synchronous reset input. It resets the transmitter when High. To fully reset the transmitter, the tx_ce_in, tx_sd_ce_in, and tx_edh_ce_in inputs must be High when tx_rst_in is asserted. |
| tx_usrclk_out | out | 1 | GTH txusrclk clock output. This port is also signal fed into tx_clk port of the UHD-SDI core |
| tx_ce_in | In | 1 | This is the clock enable input for the main portion of the transmitter data path. This is somewhat equivalent to the tx_din_rdy port of the old core. It must be High in SD, HD, and 3GA modes. In 3GB mode, it must have a 50% duty cycle. In 6G and 12G modes, it must have a 100% duty cycle when four streams are interleaved, 50% duty cycle when eight streams are interleaved, and 25% duty cycle when all 16 data streams are interleaved. |
| tx_sd_ce_in | In | 1 | This is the clock enable for SD-SDI mode. It must have exactly a 5|6|5|6 cadence in SD-SDI mode and must be High in all other modes. |
| tx_edh_ce_in | In | 1 | This is the clock enable for the TX EDH processor. In SD-SDI mode, it must be exactly equal to the tx_sd_ce port with its 5|6|5|6 cadence. It must be phase aligned with tx_sd_ce_in. In all other modes, this ce can be driven Low to reduce the power that would be consumed by the EDH processor. |
| tx_mode_in | In | 3 | This input port is used to select the transmitter SDI mode: 000 = HD 001 = SD 010 = 3G 100 = 6G 101 = 12G All other values are reserved. |
| tx_m_in | In | 1 | This port is used to select which reference clock to use. By convention, 0 = select 148.35 MHz refclk, 1 = select 148.5 MHz refclk. However, this distinction is entirely governed by the frequency of the PLLs and the values set to the TXPLLCLKSEL_TX_M_0 and TXPLLCLKSEL_TX_M_1 parameters in this table. |
| tx_insert_crc_in | In | 1 | When this input is High, the transmitter generates and inserts CRC values into the data streams for each video line in all modes except SD-SDI. When this input is Low, CRC values are not inserted into the data streams. This input is ignored in SD-SDI mode. |
| tx_insert_ln_in | In | 1 | When this input is High, the transmitter inserts line numbers into all active data streams after the EAV of each video line. The line numbers must be supplied on the tx_line_chX_in input ports of all active data stream pairs. When this input is Low, line numbers are not inserted. This input is ignored in SD-SDI mode. |
| tx_insert_st352_in | In | 1 | When this input is High, ST 352 packets are inserted into the data streams, otherwise the packets are not inserted. ST 352 packets are mandatory in 3G, 6G, and 12G modes and optional in HD and SD modes. |
| tx_overwrite_st352_in | In | 1 | If this input is High, ST 352 packets already present in the data streams are overwritten. If this input is Low, existing ST 352 packets are not overwritten. |
| tx_insert_edh_in | In | 1 | When this input is High, the transmitter generates and inserts EDH packets into every field in SD-SDI mode. When this input is Low, EDH packets are not inserted. This input is ignored in all modes except SD-SDI mode. |
| tx_mux_pattern_in | In | 3 | This specifies the data stream interleaving pattern to be used. 000 = SD, HD, and 3G level A 001 = 3G level B 010 = 8 stream interleave in 6G and 12G modes 011 = 4 stream interleave in 6G mode 100 = 16 stream interleave in 12G mode |
| tx_insert_sync_bit_in | In | 1 | In 6G and 12G modes, when this port is High, the sync bit insertion function is enabled for run length mitigation. For compliance with the ST 2081 and ST 2082 standards, sync bit insertion must be enabled. However, some early implementations of 6G-SDI and 12G-SDI receivers do not support sync bit insertion and when transmitting signals to those devices, sync bit insertion can be disabled when setting this port Low. |
| tx_line_0_in | In | 11 | Current line number for data streams 1 & 2 |
| tx_line_1_in | In | 11 | Current line number for data streams 3 & 4 |
| tx_line_2_in | In | 11 | Current line number for data streams 5 & 6 |
| tx_line_3_in | In | 11 | Current line number for data streams 7 & 8 |
| tx_line_4_in | In | 11 | Current line number for data streams 9 & 10 |
| tx_line_5_in | In | 11 | Current line number for data streams 11 & 12 |
| tx_line_6_in | In | 11 | Current line number for data streams 13 & 14 |
| tx_line_7_in | In | 11 | Current line number for data streams 15 & 16 |
| tx_st352_line_f1_in | In | 11 | The ST 352 packets are inserted into the HANC space of the line number specified by this input port. For interlaced video, this input port specifies a line number in field 1. For progressive video, this specifies the only line in the frame where the packets are inserted. The input value must be valid during the entire HANC interval. If tx_insert_st352 is Low, this input is ignored. |
| tx_st352_line_f2_in | In | 11 | For interlace video, ST 352 packets are inserted on the line number in field 2 indicated by this value. For progressive video, this input port must be disabled by driving the tx_st352_f2_en port Low. The input value on this port must be valid during the entire HANC interval. This port is ignored if either tx_insert_st352 or tx_st352_f2_en are Low. |
| tx_st352_f2_en_in | In | 1 | This input controls whether or not ST 352 packets are inserted on the line indicated by tx_vpid_line_f2. For interlaced video, this input must be High if ST 352 packet insertion is enabled. For progressive video, this input must be Low if ST 352 packet insertion is enabled. If ST 352 packet insertion is disabled (tx_insert_st352 = Low), this port is ignored. |
| tx_st352_data_0_in | In | 32 | The four data bytes of the ST352 packet to be inserted into ds1 when tx_insert_st352 is High. The data bytes are ordered like this: {byte4, byte3, byte2, byte1}. |
| tx_st352_data_1_in | In | 32 | The four data bytes of the ST352 packet to be inserted into ds3 when tx_insert_st352 is High. In 3GA mode, this port specifies the data bytes that are inserted into the ST352 packet of ds2. |
| tx_st352_data_2_in | In | 32 | The four data bytes of the ST352 packet to be inserted into ds5 when tx_insert_st352 is High. |
| tx_st352_data_3_in | In | 32 | The four data bytes of the ST352 packet to be inserted into ds7 when tx_insert_st352 is High. |
| tx_st352_data_4_in | In | 32 | The four data bytes of the ST352 packet to be inserted into ds9 when tx_insert_st352 is High. |
| tx_st352_data_5_in | In | 32 | The four data bytes of the ST352 packet to be inserted into ds11 when tx_insert_st352 is High. |
| tx_st352_data_6_in | In | 32 | The four data bytes of the ST352 packet to be inserted into ds13 when tx_insert_st352 is High. |
| tx_st352_data_7_in | In | 32 | The four data bytes of the ST352 packet to be inserted into ds15 when tx_insert_st352 is High. |
| tx_ds1_in | In | 10 | Data stream 1 input: SD=Y/C, HD=Y, 3GA=DS1(Y), 3GB=AY, 6G/12G=DS1 |
| tx_ds2_in | In | 10 | Data stream 2 input: HD=C, 3GA=DS2(C), 3GB=AC, 6G/12G=DS2 |
| tx_ds3_in | In | 10 | Data stream 3 input: 3GB=BY, 6G/12G=DS3 |
| tx_ds4_in | In | 10 | Data stream 4 input: 3GB=BC, 6G/12G=DS4 |
| tx_ds5_in | In | 10 | Data stream 5 input: 6G/12G=DS5 |
| tx_ds6_in | In | 10 | Data stream 6 input: 6G/12G=DS6 |
| tx_ds7_in | In | 10 | Data stream 7 input: 6G/12G=DS7 |
| tx_ds8_in | In | 10 | Data stream 8 input: 6G/12G=DS8 |
| tx_ds9_in | In | 10 | Data stream 9 input: 12G=DS9 |
| tx_ds10_in | In | 10 | Data stream 10 input: 12G=DS10 |
| tx_ds11_in | In | 10 | Data stream 11 input: 12G=DS11 |
| tx_ds12_in | In | 10 | Data stream 12 input: 12G=DS12 |
| tx_ds13_in | In | 10 | Data stream 13 input: 12G=DS13 |
| tx_ds14_in | In | 10 | Data stream 14 input: 12G=DS14 |
| tx_ds15_in | In | 10 | Data stream 15 input: 12G=DS15 |
| tx_ds16_in | In | 10 | Data stream 16 input: 12G=DS16 |
| tx_ds1_st352_out | Out | 10 | This is the data stream 1 (DS1) output data stream after the ST 352 packet insertion module. The data stream is output at this point for the application to embed other ANC data. |
| tx_ds2_st352_out | Out | 10 | This is the DS2 output data stream for ANC insertion. |
| tx_ds3_st352_out | Out | 10 | This is the DS3 output data stream for ANC insertion. |
| tx_ds4_st352_out | Out | 10 | This is the DS4 output data stream for ANC insertion. |
| tx_ds5_st352_out | Out | 10 | This is the DS5 output data stream for ANC insertion. |
| tx_ds6_st352_out | Out | 10 | This is the DS6 output data stream for ANC insertion. |
| tx_ds7_st352_out | Out | 10 | This is the DS7 output data stream for ANC insertion. |
| tx_ds8_st352_out | Out | 10 | This is the DS8 output data stream for ANC insertion. |
| tx_ds9_st352_out | Out | 10 | This is the DS9 output data stream for ANC insertion. |
| tx_ds10_st352_out | Out | 10 | This is the DS10 output data stream for ANC insertion. |
| tx_ds11_st352_out | Out | 10 | This is the DS11 output data stream for ANC insertion. |
| tx_ds12_st352_out | Out | 10 | This is the DS12 output data stream for ANC insertion. |
| tx_ds13_st352_out | Out | 10 | This is the DS13 output data stream for ANC insertion. |
| tx_ds14_st352_out | Out | 10 | This is the DS14 output data stream for ANC insertion. |
| tx_ds15_st352_out | Out | 10 | This is the DS15 output data stream for ANC insertion. |
| tx_ds16_st352_out | Out | 10 | This is the DS16 output data stream for ANC insertion. |
| tx_ds1_anc_in | In | 10 | Data stream 1 (DS1) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds2_anc_in | In | 10 | Data stream 2 (DS2) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds3_anc_in | In | 10 | Data stream 3 (DS3) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds4_anc_in | In | 10 | Data stream 4 (DS4) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds5_anc_in | In | 10 | Data stream 5 (DS5) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds6_anc_in | In | 10 | Data stream 6 (DS6) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds7_anc_in | In | 10 | Data stream 7 (DS7) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds8_anc_in | In | 10 | Data stream 8 (DS8) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds9_anc_in | In | 10 | Data stream 9 (DS9) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds10_anc_in | In | 10 | Data stream 10 (DS10) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds11_anc_in | In | 10 | Data stream 11 (DS11) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds12_anc_in | In | 10 | Data stream 12 (DS12) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds13_anc_in | In | 10 | Data stream 13 (DS13) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds14_anc_in | In | 10 | Data stream 14 (DS14) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds15_anc_in | In | 10 | Data stream 15 (DS15) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_ds16_anc_in | In | 10 | Data stream 16 (DS16) input from the application’s ANC inserter. This port is only used if the tx_use_anc_in port is High. |
| tx_use_anc_in | In | 1 | When Low, the data streams out of the ST352 packet insertion function are routed internally to the TX output channels. When High, the TX output channels accept data streams from the tx_ds[16:1]_anc_in ports. |
| tx_ce_align_err_out | Out | 1 | This output indicates problems with the 5|6|5|6 clock cycle cadence of the tx_sd_ce input in SD-SDI mode. In SD-SDI mode, the tx_sd_ce signal must follow a regular 5|6|5|6 clock cycle cadence. If it does not, the SD-SDI serial stream is formed incorrectly. The tx_ce_align_err output goes High if the cadence is incorrect. This port is only valid in SD-SDI mode and only if tx_sd_bitrep_bypass is Low. |
| tx_slew_out | Out | 1 | This output is designed to control the slew rate signal of the external SDI cable equalizer. It is High when the TX mode is SD-SDI. Otherwise it is Low. |
| tx_change_done_out | Out | 1 | This output is Low during those periods when the
GTH TX is being initialized or reset or the GTH DRP registers or
txsysclksel ports are being dynamically changed. If the sequence
completes successfully, the tx_change_done_out output is asserted
High to indicate successful completion. This output is synchronous with the gth_drpclk_in. |
| tx_change_fail_out | Out | 1 | Under normal conditions, this output is always
Low. It only goes High if the control module is unsuccessful in
completing a GTH TX initialization or reset sequence or a dynamic
change of the GTH DRP or txsysclksel ports. If such a failure
occurs, the tx_change_fail_out port is asserted High and the
tx_change_fail_code port indicates the nature of the failure. If a failure occurs as indicated by tx_change_fail_out going High, a full reset must be done using the tx_rst_in and gth_wiz_reset_tx_pll_and_datapath_in. This output is synchronous with the gth_drpclk_in. |
| tx_change_fail_code_out | Out | 3 | When the tx_change_fail port is High, this port indicates the nature of the failure. See Table 1 for encoding of this port. This output is synchronous with the gth_drpclk_in. |
| DRP Controller Ports | |||
| drp_fail_out | Out | 1 | Under normal conditions, this output is always Low. It only goes High
if the control module is unsuccessful in completing a GTH DRP
transaction. If such a failure occurs, the drp_fail_out port is
asserted High and the drp_fail_cnt_out port incremented. If a failure occurs as indicated by drp_fail_out going High, a full GTH reset must be done using the gth_wiz_reset_all_in port. This output is synchronous with the gth_drpclk_in. |
| drp_fail_cnt_out | Out | 8 | This port indicates the count of how many DRP transaction attempts have failed. |
| GTH Ports for SDI Wrapper Support | |||
| gth_wiz_reset_all_in | In | 1 | User signal to reset the phase-locked loops (PLLs) and active data directions of transceiver primitives. An active-High, asynchronous pulse of at least one gth_drpclk_in period in duration initializes the process. |
| gth_wiz_reset_tx_pll_and_ datapath_in | In | 1 | User signal to reset the transmit data direction and associated PLLs of transceiver primitives. An active-High, asynchronous pulse of at least one gth_drpclk_in period in duration initializes the process. |
| gth_wiz_reset_rx_pll_and_ datapath_in | In | 1 | User signal to reset the receive data direction and associated PLLs of transceiver primitives. An active-High, asynchronous pulse of at least one gth_drpclk_in period in duration initializes the process. |
| gth_wiz_txresetdone_out | Out | 1 | Active-High indication that the transmitter
reset sequence of transceiver primitives has completed. This output is synchronous with the tx_usrclk_out. |
| gth_wiz_rxresetdone_out | Out | 1 | Active-High indication that the receiver reset
sequence of transceiver primitives has completed. This output is synchronous with the rx_usrclk_out. |
| gth_drpclk_in | In | 1 | DRP clock to GTH. Normally, this port is driven by the same clock as rx_fxdclk_in. |
| gth_qpll0_refclk_p_in | In | 1 | This port must be connected to either MGTREFCLK0P or MGTREFCLK1P FPGA input ports.This port drives the I pin of the IBUFDS_GTE3 primitive. |
| gth_qpll0_refclk_n_in | In | 1 | This port must be connected to either MGTREFCLK0N or MGTREFCLK1N FPGA input ports.This port drives the IB pin of the IBUFDS_GTE3 primitive. |
| gth_qpll0_reset_in | In | 1 | Active-High reset input to the QPLL0RESET pin of GTHE3_COMMON primitive |
| gth_qpll0_clk_out | Out | 1 | This should be connected to gth_qpll0_clk_in port of SDI Wrapper. Clock output from the QPLL0OUTCLK port of GTHE3_COMMON primitive. |
| gth_qpll0_refclk_out | Out | 1 | This should be connected to gth_qpll0_refclk_in port of SDI Wrapper. Clock output from the QLL0OUTREFCLK port of GTHE3_COMMON primitive. |
| gth_qpll0_lock_out | Out | 1 | This should be connected to gth_qpll0_lock_in port of SDI Wrapper. This active-High lock indicator of QPLL0 from the QPLL0LOCK port of GTHE3_COMMON |
| gth_qpll1_refclk_p_in | In | 1 | This port must be connected to either the MGTREFCLK0P or MGTREFCLK1P FPGA input ports. This port drives the I pin of the IBUFDS_GTE3 primitive. |
| gth_qpll1_refclk_n_in | In | 1 | This port must be connected to either the MGTREFCLK0N or MGTREFCLK1N FPGA input ports. This port drives the IB pin of the IBUFDS_GTE3 primitive. |
| gth_qpll1_reset_in | In | 1 | Active-High reset input to the QPLL1RESET pin of the GTHE3_COMMON primitive. |
| gth_qpll1_clk_out | Out | 1 | This should be connected to gth_qpll1_clk_in port of SDI Wrapper. Clock output from the QPLL1OUTCLK port of the GTHE3_COMMON primitive. |
| gth_qpll1_refclk_out | Out | 1 | This should be connected to gth_qpll1_refclk_in port of SDI Wrapper. Clock output from the QLL1OUTREFCLK port of the GTHE3_COMMON primitive. |
| gth_qpll1_lock_out | Out | 1 | This should be connected to gth_qpll1_lock_in port of SDI Wrapper. This is the active-High lock indicator of QPLL1 from the QPLL1LOCK port of GTHE3_COMMON. |
| gth_cpll_refclk_out | Out | 1 | This port is meant to be connected to the gth_cpll_refclk_in port of SDI Wrapper. Clock output from a IBUFDS_GTE3 primitive. |
| gth_cpll_lock_out | Out | 1 | This active-High frequency lock output from the CPLLLOCK port of GTHE3_CHANNEL. |
| gth_rxn_in | In | 1 | This port connects to the GTHRXN differential input pin of GTHE3_CHANNEL primitive. |
| gth_rxp_in | In | 1 | This port connects to the GTHRXP differential input pin of GTHE3_CHANNEL primitive. |
| gth_txn_out | Out | 1 | This port connects to the GTHTXN differential output pin of GTHE3_CHANNEL primitive. |
| gth_txp_out | Out | 1 | This port connects to the GTHYXP differential output pin of GTHE3_CHANNEL primitive. |
| GTH Ports for SDI Wrapper | |||
| gth_wiz_reset_all_in | In | 1 | User signal to reset the phase-locked loops (PLLs) and active data directions of transceiver primitives. An active-High, asynchronous pulse of at least one gth_drpclk_in period in duration initializes the process. |
| gth_wiz_reset_tx_pll_and_ datapath_in | In | 1 | User signal to reset the transmit data direction and associated PLLs of transceiver primitives. An active-High, asynchronous pulse of at least one gth_drpclk_in period in duration initializes the process. |
| gth_wiz_reset_rx_pll_and_ datapath_in | In | 1 | User signal to reset the receive data direction and associated PLLs of transceiver primitives. An active-High, asynchronous pulse of at least one gth_drpclk_in period in duration initializes the process. |
| gth_wiz_txresetdone_out | Out | 1 | Active-High indication that the transmitter
reset sequence of transceiver primitives has completed. This output is synchronous with the tx_usrclk_out. |
| gth_wiz_rxresetdone_out | Out | 1 | Active-High indication that the receiver reset
sequence of transceiver primitives has completed. This output is synchronous with the rx_usrclk_out. |
| gth_drpclk_in | In | 1 | DRP clock to GTH. Normally, this port is driven by the same clock as rx_fxdclk_in. |
| gth_qpll0_clk_in | In | 1 | This should be connected to gth_qpll0_clk_out port of SDI Wrapper Support. Clock input from the QPLL0OUTCLK port of GTHE3_COMMON primitive. |
| gth_qpll0_refclk_in | In | 1 | This should be connected to gth_qpll0_refclk_out port of SDI Wrapper Support. Clock input from the QPLL0OUTREFCLK port of GTHE3_COMMON primitive. |
| gth_qpll0_lock_in | In | 1 | This should be connected to gth_qpll0_lock_out port of SDI Wrapper Support. This active-High lock indicator of QPLL0 from the QPLL0LOCK port of GTHE3_COMMON. |
| gth_qpll1_clk_in | In | 1 | This should be connected to gth_qpll1_clk_out port of SDI Wrapper Support. Clock input from the QPLL1OUTCLK port of GTHE3_COMMON primitive. |
| gth_qpll1_refclk_in | In | 1 | This should be connected to gth_qpll1_refclk_out port of SDI Wrapper Support. Clock input from the QPLL1OUTREFCLK port of GTHE3_COMMON primitive. |
| gth_qpll1_lock_in | In | 1 | This should be connected to gth_qpll1_lock_out port of SDI Wrapper Support. This active-High lock indicator of QPLL1 from the QPLL1LOCK port of GTHE3_COMMON. |
| gth_cpll_refclk_in | In | 1 | Clock input for GTREFCLK0 of GTHE3_CHANNEL primitive. Normally this port is driven by a clock from IBUFDS_GTE3 primitive. |
| gth_cpll_lock_out | Out | 1 | This active-High frequency lock output from the CPLLLOCK port of GTHE3_CHANNEL. |
| gth_rxn_in | In | 1 | This port connects to the GTHRXN differential input pin of GTHE3_CHANNEL primitive. |
| gth_rxp_in | In | 1 | This port connects to the GTHRXP differential input pin of GTHE3_CHANNEL primitive. |
| gth_txn_out | Out | 1 | This port connects to the GTHTXN differential output pin of GTHE3_CHANNEL primitive. |
| gth_txp_out | Out | 1 | This port connects to the GTHYXP differential output pin of GTHE3_CHANNEL primitive. |
|
|||