Configuring FPGA with Precompiled Bit File

Implementing SMPTE SDI Interfaces with UltraScale GTH Transceivers Application Note (XAPP1248)
Document ID
XAPP1248
Release Date
2023-11-08
Revision
v1.6 English
  1. Unzip xapp1248.zip.
  2. Connect to the KCU105 via the UART USB port.
  3. Power on the KCU105.
  4. Connect to the KCU105 System Controller and set the VADJ to 1.8V.
    Note: The single microUSB connector provides access to both the Zynq system controller's UART and to the UltraScale FPGA's UART. In the Windows Device Manager, the Enhanced COM port associated with the CP210x, is the one connected to the System Controller.
  5. Open a Terminal window (115200, 8, N, 1) and set the COM port to the one communicating with the KCU105 System Controller.
  6. After the UART terminal is connected, power cycle the KCU105 to refresh the System Controller Menu in the UART terminal. Select the following option in the System Controller Menu.
  7. Adjust FPGA Mezzanine Card (FMC) Settings then in the next menu, select: Set FMC VADJ to 1.8V.
  8. Look for the VADJ power good on DS19 LED located near the power switch on the KCU105 board.
  9. Connect up the KCU105 via the JTAG USB port.
  10. In Vivado TCL Console, enter the following sequentially:
    1. cd <unzip_dir>\ready_for_download
    2. source bit_files.tcl
  11. Wait for project load and the FPGA to program.
Note: If the UHD-SDI RX is not locking, make sure that the VADJ power to FMCH port is at 1.8V VADJ power good is indicated by DS19 LED located near the power switch of the KCU105 board. If the LED is off, the VADJ power can be set through KCU105's system controller's UART interface.