Use Model 3: Multiple Transceivers Active in the Quad, All RX and TX are Dynamically Clocked by QPLL0 and QPLL1

In this use model, shown in the following figure, multiple transceivers are active in the Quad. All GTH receivers are clocked by the QPLL. All of the GTH transmitters can be independently switched between the QPLL0 and QPLL1. This model conforms to the standard use model shown in Figure 2.

In this use model, one SDI Wrapper Support is instantiated which contains the GTHE3 Common Primitive and corresponding differential clock buffers. Multiple SDI Wrappers are instantiated (up to three) for other SDI channels.

This use model covers a very common case where multiple transceivers are active in the quad, all implementing SDI interfaces. All the active GTH RX and TX units in the quad use the serial clock from the QPLL0 or QPLL1. This usage module is shown in Figure 1. This multi-link use model is the recommended clocking for both SDI TX and SDI RX if both 12G-SDI bit rate (integer and fractional) support is required. The CPLL is required to implement different protocols other than SDI in other transceivers of the same quad if less than four transceivers are used.

In this use model, the SDI Wrapper Support is designated as the QPLL0 and QPLL1 master and controls the QPLL0RESET and QPLL1RESET ports of the GTH Common Primitive. The SDI Wrappers do not control the QPLL reset, but they do monitor the QPLL0 and QPLL1 locked output of the SDI Wrapper Support.

The following connections must be made:

• Connect the reference clocks 148.5 MHz and 148.35 MHz to the gth_qpll0_refclk_p/n_in and gth_qpll1_refclk_p/n_in ports respectively.
• The gth_cpll_refclk_p_in and gth_cpll_refclk_n_in ports must be connected to zero.
• The gth_drpclk_in must be connected to the clock specified during GTH Wizard IP generation. In this application note it is 27 MHz.
• The gth_wiz_reset_tx_pll_and_datapath_in and gth_wiz_reset_rx_pll_and_datapath_in input ports must be Low only when the reference clock source to the QPLL0 and QPLL1 are stable.
• The RXPLLCLKSEL_RX_M_0 parameter of the SDI Wrapper Support and SDI Wrapper must be set to 2'b11 (QPLL0).
• The RXPLLCLKSEL_RX_M_1 parameter of the SDI Wrapper Support and SDI Wrapper must be set to 2'b10 (QPLL1).
• The TXPLLCLKSEL_TX_M_0 parameter of the SDI Wrapper Support and SDI Wrapper must be set to 2'b11 (QPLL0).
• The TXPLLCLKSEL_TX_M_1 parameter of the SDI Wrapper Support and SDI Wrapper must be set to 2'b10 (QPLL1).
• When the QPLL0 must be reset due to a reference clock change or interruption, assert the gth_qpll0_reset_in input of the SDI Wrapper Support.
• When the QPLL1 must be reset due to a reference clock change or interruption, assert the gth_qpll1_reset_in input of the SDI Wrapper Support.
• The SDI Wrapper Support qpll0/1_clk, qpll0/1_refclk and qpll0/1_lock output ports must be connected to their corresponding ports in the SDI Wrapper.