This demonstration application includes a pair of SDI RX and SDI TX interfaces on KCU105 evaluation board. It requires a Fidus 12G-SDI FMC board connected to the HPC FMC connector of the KCU105 board. The example design has a single UHD-SDI transmitter driven by a test pattern generator. It supports operation at SD-SDI, HD-SDI, 3G-SDI (levels A and B), 6G-SDI, and 12G-SDI. The UHD-SDI transmitter is controlled by a Vivado Analzyer VIO module. The example design also has a single UHD-SDI receiver which can operate in the same modes as the transmitter. The status of the UHD-SDI receiver is monitored by a Vivado Analyzer VIO module. The data streams, line numbers, and video timing signals output by the UHD-SDI receiver are captured by a Vivado Analyzer ILA module and can be inspected in the Vivado Analyzer tool.
The SDI TX is driven by a Video Test Pattern Generator. The SDI mode, the video format and video pattern of SDI TX can be selected using the Vivado VIO window in the Vivado Hardware Manager. The status of the SDI RX can be monitored using another Vivado VIO window and the video data received by the SDI RX can be captured and viewed using a Vivado ILA window.
The inrevium SDI FMC board has five connectors for the SDI interfaces. The two
connectors at the right most (Figure 2) are the
only unidirectional SDI interfaces, the right-most being the CH0 TX and the other CH0
RX. These connectors are the only ones which are used in this demonstration. The second,
third, and fourth SDI interfaces have only a single connector each, CH1, CH2 and CH3.
These are bidirectional interfaces and can be controlled by F_CHn_DIR pins of the FMC card.
The following figure is a block diagram of the demonstration, showing SDI channel 0 which is connected to the first GTH transceiver in the quad.
The inrevium SDI FMC board has 148.5 MHz and 148.5/1.001 MHz oscillators which this demo uses to supply reference clocks to the QPLL0 and the QPLL1 that goes to each transceiver. The 148.5 MHz reference clock is used by the QPLL0 and the 148.5/1.001 MHz reference clock is used by the QPLL1. The GTH transmitters are dynamically switched between the serial clock from the QPLL0 and the QPLL1 to support all SDI bit rates.
The LMH1983 device on the inrevium board supplies a 27 MHz clock to the UltraScale FPGA that is used for the DRP clock and fixed frequency clock required by the control module. To make it simplify scaling the SDI interface up to four in this demo, a four SDI channel wrapper (kugth_uhdsdi_4ch_wrapper.v) was created which instantiates one SDI Wrapper Support and three SDI Wrapper. The video generator, main, and RX Vivado VIOs were all placed inside a Verilog Generate statement to easily increase the number of channels.
The following are required to run the quad SDI demonstration:
- AMD Kintex™ UltraScale™ FPGA KCU105 Evaluation Kit
- inrevium Fidus TB-FMCH-12GSDI SDI FMC
- Two HD-BNC to BNC converter cables
- SDI signal source
- SDI signal sink (waveform monitor or other device to view signal from SDI transmitters)
- AMD Vivado IDE
The inrevium SDI FMC board must be connected to the FMC HPC connector on the KCU105 board as shown in the following figure:
The Vivado Hardware Manager must be opened to control the SDI transmitters and to look at the status and received data from the SDI receivers via the VIOs. The KCU105 board must be connected to a PC by the USB JTAG cable provided with the board. While launching the Hardware manager, make sure the JTAG clock should not be more than 30 MHz.
The configuration file named kcu105_uhdsdi_demo.bit is provided with this application note must be loaded into the Kintex UltraScale FPGA on the KCU105 board using Vivado Hardware Manager. After this, the hardware (LTX) configuration file is loaded where three HW_VIOs and an HW_ILA automatically open. A Vivado project file (bit_files.xpr) is provided with this application note so that the HW_VIOs appear as shown in Figure 1 instead of default HEX or binary view. Follow the instructions in Configuring FPGA with Precompiled Bit File to open the bit_files.xpr and to download the precompiled bitstream.