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Reference Design Matrix
The following checklist indicates the tool flow and verification procedures used for the provided reference design.
| Parameter | Description |
|---|---|
| General | |
| Developer name | Advanced Micro Devices, Inc. |
| Target devices | UltraScale devices with GTH transceivers |
| Source code provided | Yes |
| Source code format | Verilog |
| Design uses code/IP from existing application note/reference design, IP catalog, or third party | Yes, IP cores from Vivado IP catalog |
| Simulation | |
| Functional simulation performed | No |
| Timing simulation performed | No |
| Test bench used for functional and timing simulations | None |
| Test bench format | N/A |
| Simulator software/version used | N/A |
| SPICE/IBIS simulations | N/A |
| Implementation | |
| Synthesis software tools/version used | Vivado Design Suite 2023.1 |
| Implementation software tools/version used | Vivado Design Suite 2023.1 |
| Static timing analysis performed | Yes |
| Hardware Verification | |
| Hardware verified | Yes |
| Hardware platform used for verification | KCU105 and TB-FMCH-12GSDI boards |