Test Bench - 5.0 English

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

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5.0 English

This chapter contains information about the test bench provided in the Vivado® Design Suite.

This Figure and This Figure show the demonstration test bench with a SelectIO™ interface and an Aurora interface, respectively.

Figure 6-1: Demonstration Test Bench Block Diagram

X-Ref Target - Figure 6-1

Figure 6-2: Demonstration Test Bench with Aurora Interface

X-Ref Target - Figure 6-2


To demonstrate the AXI Chip2Chip core, an instance of AXI Chip2Chip core in complementary mode is connected to the AXI Chip2Chip core in the example design.

The demonstration test bench performs the following tasks:

Generates input clock signals.

Applies a reset to the example design.

Waits for one of the interrupt signals (Link Status and Multi-Bit Error) to be asserted. If Link status is asserted, a stable link is established between the Master and Slave AXI Chip2Chip cores. If Configuration Error or Multi-Bit Error is asserted, the test bench fails with Error: Link Not Detected .

If a link is successfully established, Link detected is displayed in the console.

The traffic generator starts generating fixed traffic patterns at the inputs of the AXI Chip2Chip cores.

The traffic checker checks the output signals of the AXI Chip2Chip cores against expected patterns. If the received data has an error, then error messages are issued at the console with the name, expected value and actual value of the signal in error condition.

The transactions are shown for a time interval of 10,000 ns and the test bench finishes with the Test Completed Successfully in the console.