Features - 5.0 English

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

Document ID
Release Date
5.0 English

Supports AXI4 Memory Map interface data width of 32-bit, 64-bit and 128-bit.

Supports optional AXI4-Lite data width of 32-bit

Two interface choices:

° Single Ended or Differential SelectIO™ interface

° Aurora interface that provides AXI4-Stream interface to seamlessly integrate into the Aurora IP core

Independent Master or Slave mode selection for AXI4 and AXI4-Lite interfaces

Supports Common Clock or Independent Clock operations

Supports multiple Width Conversion options for reduced I/O utilization

Supports Link Detect FSM with deskew operation for the SelectIO interface

Supports Link Detect FSM and implements Hamming SECDED error correction code (ECC) for Aurora interfaces

Allows all five AXI4 channels to operate independently

Supports an additional high-priority cut through channel for communicating interrupts

Supports completion of the pending AXI transactions in case the link fails between chip2chip master and chip2chip slave

Provides a dedicated high-priority internal channel for link status monitoring and reporting.

LogiCORE IP Facts Table

Core Specifics

Supported Device Family (1)

Versal®, UltraScale+™ Families,

UltraScale™ Architecture, Zynq®-7000,

Xilinx 7 series

Supported User Interfaces

AXI4, AXI4-Lite


Performance and Resource Utilization web page

Provided with Core

Design Files


Example Design


Test Bench


Constraints File


Simulation Model

Not Provided

S/W Driver


Tested Design Flows (2)

Design Entry

Vivado ® Design Suite


For support simulators, see th e
Xilinx Design Tools: Release Notes Guide.


Vivado Synthesis


Release Notes and Known Issues

Master Answer Record: 54806

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page


1. For a complete list of supported devices, see the Vivado® IP catalog.

2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide .